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XINT4&5 @ TMS320F28377D

Tjarco Boerkoel
Expert 1725 points

Hi All,

I have a project using both CPU cores and try to trigger interrupts XINT4 and XINT5 on CPU2 by using GPIO66.
In the 1st core I have input XBARs 13 and 14  connected to GPIO66 (INPUT13SELECT=INPUT13SELECT=66).
Then in the 2nd core I have enabled XINT4 and XINT5 with high and low polarity.
I enabled interrupt 12 in IER, and enabled the PieMember Int12.2 and int12.3 .

When toggling GPIO66 (has been verified) the interrups are not triggered. Also the Pie intterupt flags are not set for Xint5 and Xint4.
When I doe exactly the same for Xint3 (also Pie 12  member) and Xint2 then it does work.

I'm using HW revision B, are XBAR13 and XBAR14 not available on this silicon? There has been a change in headerfiles.

best regards,


Tjarco

  • 0
    TI__Genius 15260 points

    Hi Tjarco,

    It sounds like you've covered most of the items.  Can you check in the XINT4CR to see if the ENABLE bit has been set?  Also, please check in the Expressions window to make sure the writes are taking effect (some of these registers are EALLOW protected).  If all of these look OK, please post your code for configuring each of these items.

    Thanks,

    Kris