My question is regarding the external memory interface timing of the TMS320LF2407A. On page 101 of SPRS145L, rev. Sep 2007, it lists the setup time of data to the write strobe, tsu(D)W as (2H-17) nsec. In our system, H=12.5 nsec, so tsu(D)W=8nsec. However, with multiple wait states, I would expect this setup time to increase. For example, if we have two wait states (2 x 25ns), then I would expect that tsu(D)W=58nsec. Can anyone confirm if this is correct?
Also, there is another parameter for the enable time when the DSP starts driving the bus, ten(D)COL. The timing diagram on p.102 implies that the data is valid as soon as it is enabled (there is no driven, but grayed out area indicating invalid data is being driven). Normally, I would expect that the data begins being driven by the DSP after ten(D)COL, but won't necessarily be valid until tsu(D)W is satisfied. Does anyone know if this is correct?
For reads, I have a similar question regarding the parameters ta(RD) (Read data access time) and tsu(D)RD (read data setup time). If wait states are inserted to increase the time for external logic to access data, I would expect ta(RD) to increase by the amount of wait states added. Does anyone know if this is also true?
Also, on read accesses, it seems to me that tsu(D)RD is the critical time constraint to be met by the input data to the DSP, so as long as tsu(D)RD, it may not be necessary to meet ta(RD).
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