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[F28377D] PIEACK issue with CPU1 & CPU2. Default ISR will be called

Aditya BG
Expert 1825 points

Hi,

I have implemented below code and CPU2 will go to default interrupt void ADCD1_ISR(void) (File : F2837xD_DefaultISR.c) .

@ CPU1,

    EALLOW;
    DevCfgRegs.CPUSEL0.bit.EPWM3 = 1;// PWM trigger selection for ADCA, ADCB, ADCC
    DevCfgRegs.CPUSEL11.bit.ADC_A = 1;
    DevCfgRegs.CPUSEL11.bit.ADC_B = 1;
    DevCfgRegs.CPUSEL11.bit.ADC_C = 1;
    EDIS;

XINT1, XINT2 & ADCD  peripheral interrupts are used. Inside the ISR, below piece of code is used to acknowledge the PIE group

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;     //! acknowledge PIE group 1 to enable further interrupts

@ CPU2,

ADCA, ADCB & ADCC peripheral interrupts are used. Inside the ISR, below piece of code is used to acknowledge the PIE group

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;     //! acknowledge PIE group 1 to enable further interrupts


As soon as ADCA interrupt called atr CPU2, CPU will go to default ISR routine of ADCD1_ISR which is not initialized at CPU2.

At both CPU's interrupt, PIEACK_GROUP1 will be acknowledged. Is there any other method to acknowledge individually?

Could anyone help me to resolve the above problem will be highly appreciated.

thanks

Aditya B G

  • 0
    Expert 1825 points
    The above issue is resolved.
    At CPU2,
    ADCB module initialization was wrong. Instead of configuring PieCtrlRegs.PIEIER1.bit.INTx2 = 1; , i was configured PieCtrlRegs.PIEIER1.all = 0xFFFF; for ADCB module.


    Thanks
    Aditya B G