Hi,
I've searched too many posts on the forum but I could not find exact solution.
I am trying to communicate with MCP41010 digital pot through SPI of F28069. When I configured SPI as standart MISO, MOSI, CLK, CS I could not communicate with it. If I use CS as GPIO and add delays after loading data to FIFO buffer, it seems ok. Around 950 count "for loop" well suited.
My question is about here, what is the best method to control SPISTE pin?
I could not control the RX FIFO Status because, there is no returning from MCP41010 chip. I tried to find TXFIFO related method but I can't. Is there any method to control all TXFIFO buffer has sent?
Also, it would be very nice if I could set delay between last clock and SPISTEB, but I think there is no register for that purpose.
Thanks.