SPI Transmit Interrupt Not Clearing

Grant E Pitel

I have had to go through a lot of memory mapping hoops to get the TMS320 example files to work within DSP/Bios. My latest hurtle is getting SPI working.

When I enter into my SPI interrupt routine I set SpiaRegs.SPIFFTX.bit.TXFFINTCLR in order to clear the transmit interrupt. However, in my watch window I can see that SpiaRegs.SPIFFTX.bit.TXFFINT bit does not change after the command. I have seen this type of behavior before, when implementing other peripherals, from improper memory allocation. As a result, the program keeps entering the interrupt routine. I have attached except of relevant code sections below.

Please help figure out why I can not clear my interrupt. If you know of an alternative way of getting the examples to work with DSP/BIOS, please let me know, since the process is been very fustrating and time consuming. Thank you for your help.

==INTERRUPT ROUTINE (*.C)==


Void writeSpi(){
	SpiaRegs.SPIFFTX.bit.TXFFINTCLR=1;  // clear interrupt flag
	PieCtrlRegs.PIEACK.all|= M_INT6;	// issue PIE acknowledgement
}
 
==GLOBAL VARIABLE DEFS (*.C)==
#pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile");
volatile struct SPI_REGS SpiaRegs;

#pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile");
volatile struct PIE_CTRL_REGS PieCtrlRegs;
#pragma DATA_SECTION(PieVectTable,"PieVectTableFile");
struct PIE_VECT_TABLE PieVectTable;
==MEMORY MAP (*.CMD)==
SECTIONS
{
 /*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/
   PieVectTableFile  : > PIEVECT,     PAGE = 1,  TYPE = DSECT
   PieCtrlRegsFile   : > PIE_CTRL     PAGE = 1 
/*** Peripheral Frame 2 Register Structures ***/
   SpiaRegsFile      : > SPIA         PAGE = 1
}
 
==DSP/BIOS SETTINGS (*.TCF)==
/* Serial Peripheral Interface */
bios.MEM.create("SPIA");
bios.MEM.instance("SPIA").base = 0x007040;
bios.MEM.instance("SPIA").len = 0x0010;
 
/* Peripheral Interrupt Expansion */
bios.MEM.create("PIE_CTRL");
bios.MEM.instance("PIE_CTRL").base = 0x000ce0;
bios.MEM.instance("PIE_CTRL").len = 0x0020;
 
/* Interrupt Assignment */
bios.PIE.instance("PIE_INT6_1").fxn = prog.extern("readSpi");
bios.PIE.instance("PIE_INT6_1").useDispatcher = 1;
bios.PIE.instance("PIE_INT6_1").monitor = "Data Value";
bios.PIE.instance("PIE_INT6_2").fxn = prog.extern("writeSpi");
bios.PIE.instance("PIE_INT6_2").useDispatcher = 1;
bios.PIE.instance("PIE_INT6_2").monitor = "Data Value";

over 15 years ago

0 Eggi over 15 years ago

Prodigy 235 points

Hi Grant

Do you use tx fifo? On which level is it set? If you have tx fifo level at zero, the next tx interrupt appears after leaving interrupt routine.

On my delfino servo control board i also use spi and i set fifo level like this.

SpiaRegs.SPIFFTX.all=0xC028;

So interrupt appears only after 8 characters in fifo

Hope this helps

Eggi

0 Grant E Pitel over 15 years ago

Intellectual 650 points

I do have FIFO setup, but both have receive and transmit levels set to one. Good idea though.

SpiaRegs.SPIFFRX.bit.RXFFIL=1;
SpiaRegs.SPIFFTX.bit.TXFFIL=1;

Quick question. If you add SpiaRegs.SPIFFTX.bit.TXFFINT as a watch variable, does it go to zero immediately following the command:

SPIFFTX.bit.TXFFINTCLR=1;

If it does, this verifies something is not working on my end. If it doesn't, I know I am misinterpreting how the FIFO SPI modules works. Thanks.

0 yang zou over 14 years ago in reply to Grant E Pitel

Prodigy 210 points

Did you slove where the issue is?I have the same questions,and when i write some bytes to FIFO,SpiaRegs.SPIFFTX.TXFFST is always zero.

After executing SPIFFTX.bit.TXFFINTCLR=1; the TXFFINT is still 1,it donnot be cleared.So why?

I need your help,thanks a lot for your help!

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SPI Transmit Interrupt Not Clearing