SCI Boot Configuration of F28377D

Hi,

Is this chosen of options determined by the user?

Yes, it's determined by user.

 If is, how to configure?

This is done by configuring the Zx-BOOTCTRL location in USER OTP. This location is part of security setting in USER OTP and can be programmed independently using CCS flash plug-in or by flash API. Please note that since this location is in OTP and ECC enabled, it can be programmed only once so user has to be very careful while programming this. If incorrect value get programmed then value can not be changed and user may have to replace the part.

Please refer "Table 3-4. BOOTCTRL Register Bit Definition for CPU1" and "Table 3-6. Get Mode Decoding on CPU1" in TRM for definition of this register location.

Regards,

Vivek Singh

Hi, Vivek

My understanding is that the Zx-BOOTCTRL configuration only changes the boot mode pins which are GPIO84 and GPIO72 as default setting. In other words, OPT_BOOTPIN0 picks the boot mode pin 0, and OPT_BOOTPIN1 picks the boot mode pin 1.

My question is how to configure the SCI BOOT pins as there are two options(option 1 with GPIO84 and GPIO85, option2 with GPIO28 and GPIO29). I noticed that there are also two SCI BOOT mode In Table 3-6. Get Mode Decoding on CPU1 named SCI BOOT0 and SCI BOOT1. Is SCIBoot IO Option 1 corresponding to SCI BOOT 0 and SCIBoot IO Option 2 corresponding to SCI BOOT 1?

Thanks!

Please refer to Pg532 Table 3-4 of F28377D TRM. BOOTCTRL allows the user to configure boot mode pins and OTP_BMODE which defines the boot mode selected when the boot mode is getmode option.

Also refer to page538 (Figure3-4) for more details about OTP address and the flow chart for more details.

Regards,
Manoj

Hi, Manoj

Now there are two methods to configure CPU1 of F28377D in SCI BOOT mode.
Method 1:
Configure boot mode pin 1 = 0, boot mode pin 0 = 1(Table 3-1). This is SCI mode.
Method 2:
Configure boot mode pin 1 = 1, boot mode pin 0 = 1(Table 3-1). This is get mode. Then configure OTP_MODE = 0x01(SCI BOOT0) or OTP_MODE = 0x81(SCI BOOT1). For SCI BOOT0, it uses GPIO84 as SCITX pin and GPIO85 as SCIRX pin; FOR SCI BOOT1, it uses GPIO29 as SCITX pin and GPIO28 as SCIRX pin.
Here are the questions:
1. For method 1, which pins will the device use as SCITX and SCIRX pin as it just said SCI mode without explicit option?
2. According to Table 3-7(on page 533), there is no SCI boot mode option for CPU2 when configured as get mode. So is it possible to configure CPU2 to SCI boot mode? If yes, how?

Sorry missed to add 1 more setup

a) Connect SCIA to CPU2 using CPUSEL

So if I want to program CPU2's flash using SCI boot mode(like C2Prog flash programming tool), CPU1 must have appropriate application code firstly.
For CPU2 SCI boot mode, SCITX (GPIO84) & SCIRX (GPIO85) are used?

Hi, Manoj

According to CPU2 Flow chart as shown below, if ZxBOOTCTRL.OTP_KEY==0x5A and ZxBOOTCTRL.OTP_BMODE == FLASH_BOOT, then CPU2 will enter FLASH BOOT mode but not WAIT BOOT mode. In this case, SCI boot is not implemented. As ZxBOOTCTRL register is programmed only once, this means CPU2 will always branch to FLASH BOOT or WAIT BOOT mode, and switching between this two boot modes is not allowed.

For normal operation, CPU2 boots from FLASH. When CPU2 needs to be reprogrammed by FLASH programming tool(like C2Prog), CPU2 should boot from SCI.

So how to implement this requirement?

Hi,

There are different Zx_BOOTCTRL locations for for CPU1 and CPU2. I am assuming you are programming the one for CPU1 and not of CPU2 hence it does not impact the operation of CPU2.

Regards,
Vivek Singh

Hi,

I have noticed that each CPU has its own ZxBOOTCTRL registers. But the question I mentioned above is focusing on CPU2.  Let's make it clearly. "According to CPU2 Flow chart, if ZxBOOTCTRL.OTP_KEY of CPU2 ==0x5A and ZxBOOTCTRL.OTP_BMODE of CPU2 == FLASH_BOOT, then CPU2 will enter FLASH BOOT mode but not WAIT BOOT mode. In this case, SCI boot is not implemented. As ZxBOOTCTRL register of CPU2 is programmed only once, this means CPU2 will always branch to FLASH BOOT or WAIT BOOT mode, and switching between this two boot modes is not allowed."

Hi,Vesgine,
If Factory default Options, and GPIO72=0,GPIO84=1, SCI Mode Boot .
Does bootloader use option 1 with GPIO84 and GPIO85, or option2 with GPIO28 and GPIO29?
Thanks.

Hi,Vesgine,
If Factory default Options, and GPIO72=0,GPIO84=1, SCI Mode Boot .
Does bootloader use option 1 with GPIO84 and GPIO85, or option2 with GPIO28 and GPIO29?
Thanks.

Hi,

That's correct.

Regards,

Vivek Singh

Here is the question:
For normal operation, CPU2 boots from FLASH. When CPU2 needs to be reprogrammed by FLASH programming tool(like C2Prog), CPU2 should boot from SCI.

So how to implement this requirement?

As Manoj said before, GPIO84 and GPIO85 is used.

Hi,

For such case you need to use the method suggested by Manoj. You need to have CPU1 application code which can BOOT the CPU2 differently based on some GPIO input or any other command received over communication channel.

Regards,
Vivek Singh

Hi,

Question 1:

For new devices, the factory value of Zx-BOOTCTRL registers are 0xFFFFFFFF. According to the CPU2 flow chart, CPU2 will enter WAIT BOOT mode(because Zx-BOOTCTRL.OTP_KEY != 0x5A). If the CPU1 application doesn't send any boot command to CPU2 by IPC, does that mean CPU2 will never startup?

Question 2:

There are two kinds of registers namely DCSM_Z1_OTP and DCSM_Z1_REGS as shown below.

Is Z1_BOOTCTRL register memory-mapped of Z1OPT_BOOTCTRL register?

What's the relationship between Z1OPT_LINKPOINTx and Z1_LINKPOINTER?

Hi,

If I configure GPIO28 & GPIO29 as SCI in CPU1 application, can I use SCIBoot – IO Option 2 (GPIO28 & GPIO29) for CPU2? Thank you

Regards,


Kevin

Hello Kevin,

Please consider creating a new post if the discussion on this thread doesn't answer your question. This post had been closed a while ago and is no longer tracked. You can provide the necessary information regarding your issue in the new post and include a link to this post if you'd like.

Thanks,
Elizabeth

Hi Kevin,

CPU2 peripheral BOOT is controlled by user application code hence user should be able to set the proper pinmuxing for SCI boot in their CPU1 application code and BOOT CPU2 accordingly.

Regards,

Vivek Singh