This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

About ADC Acquisition Window

Dear All

The Doc (TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator) 

What the "The total sampling time is found by adding the sample window size to the conversion time of the ADC, 13 ADC clocks." means?

Thanks for any helps.

Hank

The original contents:

1.3.1 ADC Acquisition (Sample and Hold) Window
External drivers vary in their ability to drive an analog signal quickly and effectively. Some circuits require
longer times to properly transfer the charge into the sampling capacitor of an ADC. To address this, the
ADC supports control over the sample window length for each individual SOC configuration. Each
ADCSOCxCTL register has a 6-bit field, ACQPS, that determines the sample and hold (S/H) window size.
The value written to this field is one less than the number of cycles desired for the sampling window for
that SOC. Thus, a value of 15 in this field will give 16 clock cycles of sample time. The minimum number
of sample cycles allowed is 7 (ACQPS=6). The total sampling time is found by adding the sample window
size to the conversion time of the ADC, 13 ADC clocks. Examples of various sample times are shown
below in Table 1.

  • Hi,

    Yes, the table that has not been included has the actual acquisition window time (depending on the ACQPS value) that needs to be added to ADC conversion time.

    Regards,
    Gautam
  • Hi Hank,


    The S+H window is the time that the S+H switch is open and the voltage on the ADC pin is allowed to charge the internal S+H capacitor.  This is (ACQPS + 1) ADCCLKs.

    The conversion time is the period where the voltage captured on the S+H capacitor is measured to produce a digital output.  This is 13 ADCCLKs.

    The total time to sample a voltage is therefore (ACQPS + 1) + 13.  Note that depending on what mode the ADC is in (overlap vs. non-overlap) subsequent conversions can be somewhat pipe-lined.  In this case, up to 7 cycles of the next conversion's S+H duration may overlap with the conversion phase of the previous conversion.