ADS8328 sound bleeding over to other channel TMS320F28335

I have an ADS8328 hooked up to the McBSP of my TMS320F28335 and am using it to read in from two different audio sources. I have designed a small library that initializes the device into Manual Trigger, Manual Channel Select mode and allows me to read from a given channel (0 or 1) and write to it to configure. 

For some reason, when I try to read in from one channel and then immediately read in from the other channel. The sounds of one channel bleeds into another. This makes me wonder if I have a timing issue and if I am actually getting a correct signal for even one  channel. I was wondering if someone could look at my library and see if something looks off.

Here is my write function:

// Writes a value to the ADC
static void ADS8328_Write(unsigned int value)
{
	while(!McbspbRegs.SPCR2.bit.XRDY);	// Wait until transmit register is ready
	McbspbRegs.DXR1.all = value;
}

Here is my initialization:

// Initializes the ADS8328 to run in manual trigger, manual channel selection.
unsigned int ADS8328_Init()
{
	EALLOW;
	GpioCtrlRegs.GPAMUX2.all &= 0xFF00FFFF;	//clear location for MCBSP
	GpioCtrlRegs.GPAMUX2.all |= 0x00FF0000;	//select MDRB,MDXB,MCLKXB,MFSXB

	McbspbRegs.SPCR2.all=0x0000;		// Reset FS generator, sample rate generator & transmitter
	McbspbRegs.SPCR1.all=0x0000;		// Reset Receiver, Right justify word

	McbspbRegs.SPCR1.bit.CLKSTP = 2;		// Set to clock stop mode
	McbspbRegs.PCR.bit.CLKXP = 0;        // CPOL = 0, CPHA = 0 rising edge no delay
	McbspbRegs.PCR.bit.CLKRP = 0;

	McbspbRegs.PCR.bit.CLKXM = 1;		// CLKX generated internally, CLKR derived from an external source
	McbspbRegs.PCR.bit.SCLKME = 0;
	McbspbRegs.SRGR2.bit.CLKSM = 1;		// CLKSM=1 (If SCLKME=0, i/p clock to SRG is LSPCLK)
	McbspbRegs.SRGR1.bit.CLKGDV = 1;	// CLKG frequency = LSPCLK/(CLKGDV+1)
	McbspbRegs.PCR.bit.FSXM = 1;		// FSX generated internally, FSR derived from an external source
	McbspbRegs.SRGR2.bit.FSGM = 0;		// FSX pulses every time data is transferred from DXR1 to XSR1
	McbspbRegs.PCR.bit.FSXP = 1;		// FSX is active low

	McbspbRegs.XCR2.bit.XDATDLY = 1;	// Transfer delay = 1 (for master mode)
	McbspbRegs.RCR2.bit.RDATDLY = 1;	// Recieve delay = 1 (for master mode)

	McbspbRegs.XCR1.bit.XFRLEN1 = 0;	// transmit frame length = 1 word
	McbspbRegs.XCR1.bit.XWDLEN1= 2;     // 16-bit word

	McbspbRegs.RCR1.bit.RFRLEN1 = 0;	// recieve frame length = 1 word
	McbspbRegs.RCR1.bit.RWDLEN1= 2;     // 16-bit word

	McbspbRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
	delay_loop();                // Wait at least 2 SRG clock cycles
	McbspbRegs.SPCR2.bit.XRST=1; // Release TX from Reset
	McbspbRegs.SPCR1.bit.RRST=1; // Release RX from Reset
	delay_loop();
	McbspbRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
	delay_loop();

	GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 0;	// GPIO8  is the INT signal
	GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 0; // GPIO9 is the CONVST signal
	GpioCtrlRegs.GPADIR.bit.GPIO8 = 0;
	GpioCtrlRegs.GPADIR.bit.GPIO9 = 1;
	GpioDataRegs.GPADAT.bit.GPIO9 = 1;

	ADS8328_Write(0xE7BD);			// sets mode to use
	delay_loop();

	EDIS;

	return 0;
}

Here is my read function:

// Reads a channel of the ADC
int ADS8328_Read(channel c)
{
	ADS8328_Write(c);					// select channel
	while(!McbspbRegs.SPCR1.bit.RRDY);     	// Master waits until RX data is ready
	GpioDataRegs.GPACLEAR.bit.GPIO9 = 1; // set CONVST low
	GpioDataRegs.GPASET.bit.GPIO9 = 1;   // set CONVST high
	while(!GpioDataRegs.GPADAT.bit.GPIO8); // Wait for trigger
	ADS8328_Write(0xD000);
	while(!McbspbRegs.SPCR1.bit.RRDY);     	// Master waits until RX data is ready

	return (McbspbRegs.DRR1.all - dcOffset);
}

Here is a case where this "bleeding" occurs

int x = ADS8328_Read(CHANNEL1);
int y = ADS8328_Read(CHANNEL0);

DAC8830_Write(x);

Here x will get filled with some audio from Channel 0

Any ideas?