I am using the McBSP in mode SPI to read a external converter (ADS1271). I configured the CPU generat interruption on every DREADY signal coming from the ADC. This interrupt will just transmit data in order the read the converter and data will be in DDR1 and DDR2.
I configured the DMA CH1 to move data from the DDR2 and DDR1 to a buffer and generates interruption and the end of the transfer.
so far the ADC interrupt is working but the DMA transfer and DMA interrupt are not working .
I really appreciate any idea to help
I attached the code .
void init_mcbsp_spi();
void mcbsp_xmit();
__interrupt void adc_drdy(void);
__interrupt void McBSP_data_received(void);
__interrupt void local_D_INTCH1_ISR(void);
void init_dma_32(void);
void start_dma(void);
void error(void);
// Place sdata and rdata buffers in DMA-accessible RAM (L5 for this example)
#pragma DATA_SECTION(rdata, "DMARAML5")
Uint16 rdata[128]; // Received Data
void main(void)
{
DeviceInit(); // Device Life support & GPIO
PieVectTable.XINT3=&adc_drdy; // ADC ready interrupt
XIntruptRegs.XINT3CR.bit.ENABLE = 1; //Enable interrupt
IER |= M_INT12; //enable INT12 at CPU level
init_dma_32(); // DMA Initialization for 32-bit transfers
start_dma();
init_mcbsp_spi();
sdata1 = 0x55aa;
sdata2 = 0xaa55;
EALLOW; // Allow access to EALLOW protected registers
PieVectTable.DINTCH1= &local_D_INTCH1_ISR;
EDIS; // Disable access to EALLOW protected registers
// Enable interrupts required for this example
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable the PIE block
PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable PIE Group 7, INT 1 (DMA CH1)
IER |= M_INT7; // Enable CPU INT group 7
EINT; // Enable Global Interrupts
ERTM; // Enable Global realtime interrupt DBGM
// Main loop to transfer 32-bit words through MCBSP in SPI mode periodically
for(;;)
{
}
void init_mcbsp_spi()
{
// McBSP-A register settings
McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter
McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word, Digital loopback dis.
McbspaRegs.PCR.all=0x0F08; //(CLKXM=CLKRM=FSXM=FSRM= 1, FSXP = 1)
McbspaRegs.SPCR1.bit.DLB = 0;
McbspaRegs.SPCR1.bit.CLKSTP = 2; // Together with CLKXP/CLKRP determines clocking scheme
McbspaRegs.PCR.bit.CLKXP = 0; // CPOL = 0, CPHA = 0 rising edge no delay
McbspaRegs.PCR.bit.CLKRP = 0;
McbspaRegs.PCR.bit.CLKXM = 1;
McbspaRegs.PCR.bit.SCLKME = 0;
McbspaRegs.RCR2.bit.RDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Receive)
McbspaRegs.XCR2.bit.XDATDLY=01; // FSX setup time 1 in master mode. 0 for slave mode (Transmit)
McbspaRegs.RCR1.bit.RWDLEN1=4; // 24-bit word
McbspaRegs.XCR1.bit.XWDLEN1=4; // 24-bit word
McbspaRegs.SRGR2.all=0x2000; // CLKSM=1, FPER = 1 CLKG periods
// McbspaRegs.SRGR1.all= 0x000F; // Frame Width = 1 CLKG period, CLKGDV=16
McbspaRegs.SRGR1.all= 0x0003; // Frame Width = 1 CLKG period, CLKGDV=4
McbspaRegs.SPCR2.bit.GRST=1; // Enable the sample rate generator
delay_loop(); // Wait at least 2 SRG clock cycles
McbspaRegs.SPCR2.bit.XRST=1; // Release TX from Reset
McbspaRegs.SPCR1.bit.RRST=1; // Release RX from Reset
McbspaRegs.SPCR2.bit.FRST=1; // Frame Sync Generator reset
// PieCtrlRegs.PIEIER6.bit.INTx5 =1 ; // group6 int5 = MRINTA(enable PIE)
// McbspaRegs.MFFINT.bit.RINT=1; //RINT interrupt enable
}
void mcbsp_xmit(int a, int b)
{
McbspaRegs.DXR2.all=b;
McbspaRegs.DXR1.all=a;
}
// external ADC data ready interrupt
// read the ADC throug the McBSP in SPI mode.
__interrupt void adc_drdy(void)
{
mcbsp_xmit(sdata1,sdata2);
PieCtrlRegs.PIEACK.all = PIEACK_GROUP12;
EDIS;
}
// DMA Initialization for data size > 16-bit and <= 32-bit.
void init_dma_32()
{
EALLOW;
DmaRegs.DMACTRL.bit.HARDRESET = 1;
__asm(" NOP"); // Only 1 NOP needed per Design
// Channel 1, McBSPA Receive
DmaRegs.CH1.BURST_SIZE.all = 1; // 2 words/burst
DmaRegs.CH1.SRC_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words
DmaRegs.CH1.DST_BURST_STEP = 1; // Increment 1 16-bit addr. btwn words
DmaRegs.CH1.TRANSFER_SIZE = 63; // Interrupt every 63 bursts/transfer
DmaRegs.CH1.SRC_TRANSFER_STEP = 0xFFFF; // Decrement back to DRR2
DmaRegs.CH1.DST_TRANSFER_STEP = 1; // Move to next word in buffer after each word in a burst
DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Start address = McBSPA DRR
DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // Not needed unless using wrap function
DmaRegs.CH1.DST_ADDR_SHADOW = (Uint32) &rdata[0]; // Start address = Receive buffer (for McBSP-A)
DmaRegs.CH1.DST_BEG_ADDR_SHADOW = (Uint32) &rdata[0]; // Not needed unless using wrap function
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear sync error flag
DmaRegs.CH1.DST_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want destination wrap
DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Put to maximum - don't want source wrap
DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable channel interrupt
DmaRegs.CH1.MODE.bit.CHINTMODE = 1; // Interrupt at end of transfer
DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable peripheral interrupt event
DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_MREVTA; // Peripheral interrupt select = McBSP MRSYNCA
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
EDIS;
}
void start_dma (void)
{
EALLOW;
DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start DMA Transmit from McBSP-A
EDIS;
}
// INT7.1
__interrupt void local_D_INTCH1_ISR(void) // DMA Ch1
{
EALLOW; // NEED TO EXECUTE EALLOW INSIDE ISR !!!
DmaRegs.CH1.CONTROL.bit.HALT = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt
EDIS;
return;
}
