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Entering the Parallel IO Boot Mode for TMS320F28377D

Tomas Lehotsky
Intellectual 995 points
Other Parts Discussed in Thread: TMS320F28377D

Hi,


I have very important question about accessing parallel IO boot Mode for TMS320F28377D dual-core delfino microcontroller. In technical reference manual (www.ti.com/.../spruhm8), page 530, table 3-1 I can see that for entry the parallel IO mode I need connect the TRSTn, GPIO72 and GPIO84 signals to VSS(GND). Is it meaning, that after release the reset signal XRS I can automatically access the parallel IO mode. Am I right?


On the other hand, in the same technical reference manual I find a sentence on page 549, chapter "3.20 Boot ROM GPIO COnfigurations"  that tells: "The boot mode pins are configurable by user by programming proper OTPKEY". What does it mean? Can someone change the location of Boot mode pin to other GPIO(not 84 and 72)? Or what is the OTPKEY?

Thank you for your answers!

Best regards,

milanatik

  • 0
    TI__Guru 57255 points

    Hi,

    Yes, your understanding is correct.   After XRSn is released, the device will follow the boot flow.  One of the first things it will do is check the boot mode pins.  It will then determine which boot mode to go into.

    The first-time that the chip is programmed, the device must use GPIO72 and GPIO84 as the boot mode pins. 

    ===

    While the chip is being programmed, the OTP (one-time programmable non-volatile memory) could be programmed to edit the boot-mode pins for future boots.  Note that the OTP can only be programmed once.

    [A customer might potentially edit the boot-mode pins if they wanted to use GPIO72 and/or GPIO84's as peripherals and the peripheral's function (or circuitry connected to it) would interfere with the state of the boot-mode at start up.  For instance, let's say the F28377D is to be used as a SPI slave and GPIO72 needed to be used as SPISTE because of the application's demands on the pinmux.  The state of GPIO72 at start-up may not be deterministic, since it is controlled by the external master, which would be a problem unless the boot-mode pins were changed via the OTP]


    Thank you,
    Brett

  • 0 in reply to Brett Larimore
    Intellectual 995 points
    Hi Brett,

    thank you for your answer! I will continue in this thread with additional question about Parallel IO Boot mode.

    I have found the discrepancy in Technical Reference Manual (www.ti.com/.../spruhm8) for Parallel Boot Mode data I/O signal definition. When you look to mentioned manual, on page 569, chapter "3.25.7 Parallel Boot Mode" you can see, that in figure 3-20 is description for Data GP I/O pins as [63-58,64,65]. However in the first sentence of this chapter you can see that this data bus is defined like pins GPIO0-GPIO5,GPIO8, GPIO9. Also on table 3-22 there is used this signal definition. Which data GP I/O definition is correct?

    Thank you!
    Best regards,

    milanatik
  • 0 in reply to Tomas Lehotsky
    TI__Guru 57255 points

    Since I assume the below new thread has been created for your new question (or at least is very similar), let's close this thread.
    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/481295


    Thank you,
    Brett