Other Parts Discussed in Thread: TMS320F28069
I am using the eCAP Module with a TMS320F28069 and I seem to be missing the first edge sometimes, I do not get an interrupt for the first event.
When we reset our system, our system will send out a couple of resets back to back and the CPU will end up getting reinitialized a couple of times within a second or two. On the first initialization, if the input to the eCAP is low, the eCAP is setup to look for a rising edge for the first event. Then a second or two later our system will send out a second reset event and at this point the input to the eCAP will be high, so the eCAP is setup now to look for a falling edge first. When this sequence happens, I do not get an interrupt for the first edge. If the input to the eCAP is always high for the first and second initializations, and the eCAP is setup to look for a falling edge both times, this seems to always work.
Before I initialize the eCAP, I set the input to a GPIO first and read what state the line is at, high or low. This way I know what event to look for first, a falling or rising edge. When it does not work, the first eCAP event that gets triggered by the interrupt is event 2, not event 1. So it looks like event 1 did occur, I just did not get an interrupt for it. After it starts to work, it is fine thereafter, I just don’t get an interrupt for every edge.
Any ideas what can be happening?
Below is how the eCAP is being setup -
// GPIO24 AC SIGNAL
GpioCtrlRegs.GPAMUX2.bit.GPIO24 = 1; // eCAP1
ECap1Regs.ECEINT.all = 0; // Disable all eCAP interrupts
ECap1Regs.ECCTL1.bit.CAPLDEN = 0; // Disabled loading of capture results
ECap1Regs.ECCTL2.bit.TSCTRSTOP = 0; // Stop the counter
ECap1Regs.TSCTR = 0; // Clear the counter
ECap1Regs.CTRPHS = 0; // Clear the counter phase register
// Capture Control Reg 1
if (eCAP_Input == High)
ECap1Regs.ECCTL1.bit.CAP1POL = 1; // 0 Capture Event 1 Polarity select - Falling Edge
else
ECap1Regs.ECCTL1.bit.CAP1POL = 0; // 0 Capture Event 1 Polarity select - Rising Edge
ECap1Regs.ECCTL1.bit.CTRRST1 = 0; // 1 Counter Reset on Capture Event 1 - No Reset
if (eCAP_input== High)
ECap1Regs.ECCTL1.bit.CAP2POL = 0; // 2 Capture Event 2 Polarity select - Rising Edge
else
ECap1Regs.ECCTL1.bit.CAP2POL = 1; // 2 Capture Event 2 Polarity select - Falling Edge
ECap1Regs.ECCTL1.bit.CTRRST2 = 1; // 3 Counter Reset on Capture Event 2 - Reset
ECap1Regs.ECCTL1.bit.CAP3POL = 0; // 4 Capture Event 3 Polarity select
ECap1Regs.ECCTL1.bit.CTRRST3 = 0; // 5 Counter Reset on Capture Event 3
ECap1Regs.ECCTL1.bit.CAP4POL = 0; // 6 Capture Event 4 Polarity select
ECap1Regs.ECCTL1.bit.CTRRST4 = 0; // 7 Counter Reset on Capture Event 4
ECap1Regs.ECCTL1.bit.CAPLDEN = 0; // 8 Enable Loading CAP1-4 regs on a Cap Event - Disbled
ECap1Regs.ECCTL1.bit.PRESCALE = 0; // 13:9 Event Filter prescale select - Divide by 1
ECap1Regs.ECCTL1.bit.FREE_SOFT = 10; // 15:14 Emulation mode - Run Free
// Capture Control Reg 2
ECap1Regs.ECCTL2.bit.CONT_ONESHT = 0; // 0 Continuous or one-shot - Continuous
ECap1Regs.ECCTL2.bit.STOP_WRAP = 1; // 2:1 "Stop value for one-shot, Wrap for continuous", Wrap after Capture Event 2
ECap1Regs.ECCTL2.bit.REARM = 0; // 3 One-shot re-arm
ECap1Regs.ECCTL2.bit.TSCTRSTOP = 1; // 4 TSCNT counter stop
ECap1Regs.ECCTL2.bit.SYNCI_EN = 0; // 5 Counter sync-in select
ECap1Regs.ECCTL2.bit.SYNCO_SEL = 3; // 7:6 Sync-out mode
ECap1Regs.ECCTL2.bit.SWSYNC = 0; // 8 SW forced counter sync
ECap1Regs.ECCTL2.bit.CAP_APWM = 0; // 9 CAP/APWM operating mode select
ECap1Regs.ECCTL2.bit.APWMPOL = 0; // 10 APWM output polarity select
// ECAP interrupt enable
ECap1Regs.ECEINT.bit.CEVT1 = 1; // 1 Capture Event 1 Interrupt Enable
ECap1Regs.ECEINT.bit.CEVT2 = 1; // 2 Capture Event 2 Interrupt Enable
ECap1Regs.ECEINT.bit.CEVT3 = 0; // 3 Capture Event 3 Interrupt Enable
ECap1Regs.ECEINT.bit.CEVT4 = 0; // 4 Capture Event 4 Interrupt Enable
ECap1Regs.ECEINT.bit.CTROVF = 0; // 5 Counter Overflow Interrupt Enable
ECap1Regs.ECEINT.bit.CTR_EQ_PRD1 = 0; // 6 Period Equal Interrupt Enable
ECap1Regs.ECEINT.bit.CTR_EQ_CMP = 0; // 7 Compare Equal Interrupt Enable
// ECAP interrupt clear
ECap1Regs.ECCLR.bit.INT = 1; // 0 Global Flag
ECap1Regs.ECCLR.bit.CEVT1 = 1; // 1 Capture Event 1 Interrupt Flag
ECap1Regs.ECCLR.bit.CEVT2 = 1; // 2 Capture Event 2 Interrupt Flag
ECap1Regs.ECCLR.bit.CEVT3 = 1; // 3 Capture Event 3 Interrupt Flag
ECap1Regs.ECCLR.bit.CEVT4 = 1; // 4 Capture Event 4 Interrupt Flag
ECap1Regs.ECCLR.bit.CTROVF = 1; // 5 Counter Overflow Interrupt Flag
ECap1Regs.ECCLR.bit.CTR_EQ_PRD1 = 1; // 6 Period Equal Interrupt Flag
