Common Timestamp on Dual Core Delfino

ToddMullanix

I'm looking into the feasibility of having both cores of the F28377 show up System Analyzer in CCS. This would require a common timer be used to generate the timestamp for both cores. I looked at the data sheet and it looks like the timers are not common across the two cores. Is there anyway to get what I'm looking for? Note: the granularity on the timestamp should be somewhat fine.

Little background...there is the Log module in TI-RTOS. The kernel logs key events (e.g. context switches, Semaphore post, etc.). The log record contains a timestamp.

Thanks,

Todd

over 9 years ago

0 ToddMullanix over 9 years ago

TI__Guru* 96960 points

Please note we are using MIPCCOUNTERL (0x5000C) and MIPCCOUNTERH (0x5000E) for the single core timestamp.

0 Vivek Singh over 9 years ago in reply to ToddMullanix

TI__Guru** 115191 points

Hi Todd,

Apart from IPC counter, all other timers are dedicated to each CPU. Why not use CPU specific timers for single core timestamp and IPC counter to generate timestamp for both the CPU.

Regards,
Vivek Singh

0 Vivek Singh over 9 years ago in reply to Vivek Singh

TI__Guru** 115191 points

Hi Todd, Let us know if you have any further queries on this.

Regards,
Vivek Singh

0 Bradford Backus over 9 years ago

Intellectual 535 points

I am also looking for a way to synchronize timers across cores in my case on the F28M36x. This would be useful in my application particularly as the timers (M3 GPTMRs and C28 CPUTIMERs) have different limitations. I have also not yet found a solution, but will track this.

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Common Timestamp on Dual Core Delfino