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BOR specification for TMS320F28027

Ashutosh Pailwan1
Expert 2480 points


1. The BOR trip point are 2.41 to 3.135 . Dose this range indicates that there will be BOR at instant the voltage dips to 80% of 3.3 volt i.e 2.65V.  ?

2. My concern is that, is there any time delay to release or issue BOR due to small duration voltage dips/rise in power system.?

3. Also if the voltage rise above certain limit dosen't BOR occurs. i.e over-voltage trip points.?

4. Does the CPU remains OFF until and unless the voltage is below trip point condition. I mean system remains in inactive/reset mode if the voltage is beyond the range.?

5. what dose supervisor reset relases delay time means.?

  • 0
    Guru 192875 points
    Hi Ashutosh,

    Did you check this link already: e2e.ti.com/.../74329

    Regards,
    Gautam
  • 0 in reply to Gautam Iyer
    Expert 2480 points
    yes I have already gone through that link.
    It dosent give my asnwers
  • 0
    TI__Expert 7885 points
    Hi Ashutosh,

    1. The BOR trip point can be anywhere in that range (2.42V-3.135V).
    2. The speed of the BOR trip will be dependent on the rate and magnitude of the glitch. Generally seen in the nanoseconds to microseconds range at bench. If a BOR initiates a reset, the delay for the device to come back out of reset will be 400us to 800us from the time the voltage on the supply rail rises above the BOR trip voltage.
    3. There is an over-voltage BOR only on the VDD rail and only when using the internal VREG. This will trip when the internal VREG output is no longer in DS spec. We do not publish a value for this as the voltage is supplied internally and taken care of by the F28027 device.
    4. That is correct. Once the BOR is initiated, the device will not come out of reset until the voltage returns back from the BOR trip point.
    5. See #2.

    Best Regards,
    Adam Dunhoft