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Data Pointer F28377D

Cem Koose
Intellectual 880 points


Hi,

I have a fast execution rate ISR function that is linked to RAM using "ramfuncs" section in the linker file.

#pragma CODE_SECTION(ePWM_ISR, "ramfuncs");

at linker;

   ramfuncs         : LOAD = FLASHF,
                      RUN  = RAMGS14,
                      LOAD_START(_RamfuncsLoadStart),
                      LOAD_SIZE(_RamfuncsLoadSize),
                      LOAD_END(_RamfuncsLoadEnd),
                      RUN_START(_RamfuncsRunStart),
                      RUN_SIZE(_RamfuncsRunSize),
                      RUN_END(_RamfuncsRunEnd),
                      PAGE = 0, ALIGN(4)

ISR is copied into RAM at runtime using memcpy() function to speed up execution rate.

When I observe the ISR using disassembly view in CCS I see the below;

                              RamfuncsRunStart, ePWM_ISR():
01a3a8:  ...art, ePWM_ISR()+0   761B        ASP          
01a3a9:                         0005        PUSH         AR1H:AR0H
01a3aa:                         ABBD        MOVL         *SP++, XT
01a3ab:                         A8BD        MOVL         *SP++, XAR4
01a3ac:                         A0BD        MOVL         *SP++, XAR5
01a3ad:                         C2BD        MOVL         *SP++, XAR6
01a3ae:                         C3BD        MOVL         *SP++, XAR7
01a3af:                         FE08        ADDB         SP, #8
01a3b0:                         FF69        SPM          #0
01a3b1:                         2942        CLRC         OVM|PAGE0
01a3b2:                         5616        CLRC         AMODE
1127                              GPIO_TEST0_SET   = 1;
01a3b3:                         761F01FC    MOVW         DP, #0x1fc
01a3b5:                         1A020001    OR           @0x2, #0x0001
01a3b7:                         761F0340    MOVW         DP, #0x340
01a3b9:                         0A07        INC          @0x7
01a3ba:                         9207        MOV          AL, @0x7
1134                              sync_signal_counter++;
01a3bb:                         52C8        CMPB         AL, #0xc8
01a3bc:                         56C80007    BF           C$L20, LO
01a3be:                         2B07        MOV          @0x7, #0
01a3bf:                         761F01FC    MOVW         DP, #0x1fc
1138                                  Sync_Output_Toggle();
01a3c1:                         1A070020    OR           @0x7, #0x0020
                              C$L20:
01a3c3:  C$L20+0                761F0172    MOVW         DP, #0x172
1141                              Comp_LowSide_Output  = Cmpss1Regs.COMPSTS.bit.COMPLSTS;
01a3c5:                         CC020100    AND          AL, @0x2, #0x100
01a3c7:                         761F0340    MOVW         DP, #0x340
01a3c9:                         FFC7        LSR          AL, 8
01a3ca:                         9612        MOV          @0x12, AL
01a3cb:                         761F0172    MOVW         DP, #0x172
1142                              Comp_HighSide_Output = Cmpss1Regs.COMPSTS.bit.COMPHSTS;
01a3cd:                         9202        MOV          AL, @0x2
01a3ce:                         761F0340    MOVW         DP, #0x340
01a3d0:                         9001        ANDB         AL, #0x1
01a3d1:                         9614        MOV          @0x14, AL
01a3d2:                         761F0172    MOVW         DP, #0x172

....

As it can be seen up there, for every C code line, compiler generates   a "DP" instruction. How can I prevent this?

I also tried optimization settings of CCS from 0 to 4 and speed settings to 5, but the result is same.

- CPU F28377D, CCSv6.1.2, Compiler v6.4.9

  • 0
    TI__Guru 61235 points

    Hello CEM,

    The compiler is doing what it can within the coding restrictions being used and the information it has. What I mean by this is when you use the peripheral header file bit fields, the compiler generally uses direct addressing (hence DP loads). You can see that it sets the DP to 0x172 for the COMPSTS regs, but then you have other code that requires it to set DP to 0x340, then back to 0x172, and so on.

    Can you use a pointer to access whatever is on DP 0x340, or alternately setup a pointer to the COMPSTS regs? That might keep the compiler from thrashing the DP. If you can put whatever is on DP 0x340 into a structure, the compiler can probably do a nice job accessing the elements using an ARx register (pointer register) with immediate offset up to 8 elements (structure element s need to be 8 offsets at most from base address for best efficiency due to available addressing modes). You will have to play around with it and look at the compiler generated code. It sound like you know what you're doing, and know what to look for. Good luck.

    Note that if all the above fails to produce satisfactory performance, you might think about using assembly code. You said this is a high-speed ISR, which suggests it is not too long. Maybe coding by hand will not be too hard. You can even "Cheat" and use the compiler generated code as a guide. Using asm code will also avoid having to worry about code changes if you change a compiler option, or change the compiler version. You will get exactly what you code. This need for asm coding really depends on how critical the ISR speed is to you.

    Regards,
    David

  • 0 in reply to David M. Alter
    Intellectual 880 points
    Thank you Mr David, I will try your suggestions.
  • 0 in reply to Cem Koose
    TI__Guru** 115881 points
    Hi, I hope you were able to solve the issue by following the suggestion from Mr. David. Let us know if you have any further queries on this.

    Regards,
    Vivek Singh
  • 0 in reply to Vivek Singh
    Intellectual 880 points
    Hi, yes I have solved the issue by using structure pointer method suggested by Mr. David, thanks.