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How do I use the EMIF1 from the CPU2 of the F28377D?



I want to use EM1CS2  at CPU2.

So, I configurate GPIO and EMIF1 at CPU1 as follow.

<CPU1>

/*--------------------------------------------------------------------------------------------------------*/

// EM1CS2
// GPIO Mux setup

EALLOW;

// EM1 Addr. & Contorl
// EM1WE(GPIO31)
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 2; // EM1WE

// EM1CS2(GPIO34)
// EM1WAIT(GPIO36)
// EM1OE(GPIO37)
// EM1A0 ~ EM1A3(GPIO38 ~ GPIO41)
// EM1A4 ~ EM1A12(GPIO44 ~ GPIO52)
GpioCtrlRegs.GPBMUX1.all = 0xAA0AAA20; // GPIO32 ~ GPIO47
GpioCtrlRegs.GPBMUX2.all = 0x0000002A; // GPIO48 ~ GPIO63 // EM2와 겹침

// EM1 Data
// EM1D15 ~ EM1D1(GPIO69 ~ GPIO83)
// EM1D0(GPIO85)
// EM1A13 ~ EM1A19(GPIO86 ~ GPIO92)
GpioCtrlRegs.GPCMUX1.all = 0xAAAAA800; // GPIO64 ~ GPIO79
GpioCtrlRegs.GPCMUX2.all = 0xAAAAAAAA; // GPIO64 ~ GPIO79

EDIS;


EALLOW;

// Master Select for EMIF1:
// 00: CPU1 is master but not grabbed. CPU2 can grabbed the master
// ownership by changing this value to "10".
// 01: CPU1 is master.
// 10: CPU2 is master.
// 11: CPU1 is master but not grabbed. CPU2 can grabbed the master
// ownership by changing this value to "10".
Emif1ConfigRegs.EMIF1MSEL.bit.KEY = 0x93A5CE7;
Emif1ConfigRegs.EMIF1MSEL.bit.MSEL_EMIF1 = 2;

Emif1Regs.ASYNC_CS2_CR.bit.SS = 0; // 0 : normal, 1 : strobe
Emif1Regs.ASYNC_CS2_CR.bit.EW = 0; // extend wait mode disable

Emif1Regs.ASYNC_CS2_CR.bit.W_SETUP = 2; // write setup cycles
Emif1Regs.ASYNC_CS2_CR.bit.W_STROBE = 3; // write strobe cycles
Emif1Regs.ASYNC_CS2_CR.bit.W_HOLD = 2; // write hold cycles

Emif1Regs.ASYNC_CS2_CR.bit.R_SETUP = 2; // read setup cycles
Emif1Regs.ASYNC_CS2_CR.bit.R_STROBE = 3; // read strobe cycles
Emif1Regs.ASYNC_CS2_CR.bit.R_HOLD = 2; // read hold cycles

Emif1Regs.ASYNC_CS2_CR.bit.ASIZE = 1; // 16bit data bus
// asynchronous memory size

EDIS;

/*--------------------------------------------------------------------------------------------------------*/

and

CPU2 was coded as follows.

<CPU2>

/*--------------------------------------------------------------------------------------------------------*/

unsigned short *Test_EM1 = (unsigned short *)(0x00100000); //EM1CS2

.....

for(;;)

*Test_EM1 = 0x1234;

/*--------------------------------------------------------------------------------------------------------*/

But, EMIF1 CS2 did not work.

What I did wrong?

  • Hi,

    While writing to EMIF1SEL, the configuration value and KEY need to be written together else write will not go through.

    Replace following code -

    Emif1ConfigRegs.EMIF1MSEL.bit.KEY = 0x93A5CE7;
    Emif1ConfigRegs.EMIF1MSEL.bit.MSEL_EMIF1 = 2;

    With

    Emif1ConfigRegs.EMIF1MSEL.all = 0x93A5CE72;
     

    That should fix the issue.

    Regards,

    Vivek Singh

  • Thank you for your reply.
    I tried it.
    But, the result is the same.
    Please tell me another method or teaching.
  • Hi,

    Did you check if the register (EMIF1MSEL) has correct value after the write?

    Also if you use the same EMIF code for CPU1 (with EMIF1MSEL value = 0x0), does this work fine. That will make sure that EMIF configuration and board setup is fine.

    Regards,

    Vivek Singh

  • After I set the register(EMIF1MSEL) value to 0x93A5CE72, I checked the register value.
    The value is unchanged.
    (Emif1ConfigRegs.EMIF1MSEL.bit.MSEL_EMIF1 = 0)
    I don't know why ther register value do not change.

    If I use the same code for the EMIF of CPU1, it works well.
  • I did not realize that you are changing the value of MSEL_EMIF1 field from CPU1 code. This need to be done by CPU2 code. Only respective CPU can change the value for them. In this case value 0x2 means CPU2 owns the EMIF1 hence only CPU2 can change the value to 0x2. Once CPU2 is done with EMIF1 operation, it should change the value of MSEL_EMIF1 to 0x0 so that if needed, CPU1 code can change this value to 0x1.

    Following are possible state transition-

    0x0/0x3    -> 0x1   (only CPU1 code)

    0x0/0x3   -> 0x2   (only CPU2 code)

    0x1 -> 0x2 OR 0x2 -> 0x1  ( not possible)

    0x1 -> 0x0/0x3   (only CPU1 code)

    0x2 -> (0x0/0x3  ( only CPU2 code)

    Look like this info is missing in TRM. We'll update the TRM to have this detail.

    Hope this solves the issue.

    Regards,

    Vivek Singh

  • Thank you for your answer.
    I hope that TRM has been updated as soon as possible.