TZFRC PROBLEM WITH TBCTL.bit.PRDLD LOADED BY SHADOW REGISTER

Hi,

Can you also share the trip zone register configuration?
1. What is the status of one shot trip flag for EPWM4 (in TZFLG register)? Does it get cleared?
2. Can you disable phase loading for PWM4 and check the behavior?
(*ePWM[4]).TBCTL.bit.PHSEN = TB_DISABLE;

-Bharathi.

Dear Bharathi

First of all thanks for the support.

Can you also share the trip zone register configuration? 

EALLOW;
EPwm4Regs.TZSEL.bit.OSHT3 = 1; // 
EPwm4Regs.TZCTL.bit.TZA = 2; // 
EPwm4Regs.TZCTL.bit.TZB = 2; // 
EPwm4Regs.TZFRC.bit.OST = 1; // 
EDIS;

EALLOW; 

EPwm3Regs.TZSEL.bit.OSHT1 = 1; //

EPwm3Regs.TZCTL.bit.TZA = 1; // 

EPwm3Regs.TZCTL.bit.TZB = 1; // 
EPwm3Regs.TZFRC.bit.OST = 1; // 
EDIS;

1. What is the status of one shot trip flag for EPWM4 (in TZFLG register)? Does it get cleared?

Yes, it is clear when the problem happens. 

 

2. Can you disable phase loading for PWM4 and check the behavior?

(*ePWM[4]).TBCTL.bit.PHSEN = TB_DISABLE;

Using the code below it works correctly.

I included EPwm4Regs.TBCTL.bit.PHSEN = 0 after EPwm4Regs.TZFRC.bit.OST=1

EALLOW;
EPwm4Regs.TZFRC.bit.OST=1; // Habilita shutdown
EDIS;
EPwm4Regs.DBRED = 750;//150; // GARANTE DUTY CYCLE = 0 ANTES DE LIMPAR FLAG TZCLR
EPwm4Regs.DBFED = 750;//150; // O DUTY CYCLE SERA LIBERADO PELO CLA NO MODO PFM
EPwm4Regs.TBCTL.bit.PHSEN = 0;

 

I included EPwm4Regs.TBCTL.bit.PHSEN = 1before EPwm4Regs.TZCLR.bit.OST=1

EPwm4Regs.DBRED = 750;//150 // GARANTE DUTY CYCLE = 0 ANTES DE LIMPAR FLAG TZCLR
EPwm4Regs.DBFED = 750;//150; // O DUTY CYCLE SERA LIBERADO PELO CLA NO MODO PFM
EPwm4Regs.TBCTL.bit.PHSEN = 1;
EALLOW;
EPwm4Regs.TZCLR.bit.OST=1; // LIMPA FLAG TZCLR
EDIS;

Could you help me to understand how the problem happens?

the phase loading for PWM3 is always enabled -

1 - why the problem does not happen in EPWM3?

(*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW;

(*ePWM[n]).TBPRD = period;
(*ePWM[n]).CMPA.half.CMPA = period >> 1; 
(*ePWM[n]).CMPB = period >> 2;
(*ePWM[n]).TBPHS.half.TBPHS = 40;
(*ePWM[n]).TBCTR = 0;

(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UP;
(*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; 
(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;

(*ePWM[n]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
(*ePWM[n]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
(*ePWM[n]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;

(*ePWM[n]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;

(*ePWM[n]).AQCTLA.bit.ZRO = AQ_CLEAR; 
(*ePWM[n]).AQCTLA.bit.CAU = AQ_SET; 
(*ePWM[n]).AQCTLB.bit.CAU = AQ_CLEAR;
(*ePWM[n]).AQCTLB.bit.PRD = AQ_SET; 

(*ePWM[n]).DBCTL.bit.IN_MODE = DBA_ALL; 
(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; 
(*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_LOC; 
(*ePWM[n]).DBRED = 18;
(*ePWM[n]).DBFED = 18;

EALLOW;
(*ePWM[n]).TBCTL.bit.SWFSYNC = 1; 
EDIS;

2 - why the problem does not happen when EPWM4 is set to immediate PRDLD load ?

(*ePWM[4]).TBCTL.bit.PRDLD = TB_IMMEDIATE

Ricardo

Hi Ricardo,

OK. This kind of confirms what I was suspecting would be the issue. Few notes -

- It is possible that the issue could happen in Immediate mode also, it just depends on when you are making updates to TBPRD and the the value of phase you are loading.
- When you choose shadow ((*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW;) loading of new value into the TBPRD happens at the next counter zero.
- I believe, You are running in to a boundary condition where the new TBPRD value is not loaded in to EPWM4, because counter zero did not occur for EPWM4 due to phase loading. That's the reason I asked you to disable the phase loading and check the behavior and your results confirm the same.
- So you need to make sure the value of phase being loaded, status of the EPWM4 time base counter etc are proper and counter would proceed to zero and new TBPRD value takes effect.
- If the Counter of EPWM4 never reaches to zero - new period value will not be loaded and the counter may continue to keep counting and no PWM output will be generated during those cycles.

-Bharathi.

Ricardo,

I think it's possible the issue could occur with the above configuration.

"(*ePWM[3]).TBPRD and (*ePWM[4]).TBPRD are adjusted with the same value in real-time in the range between 210 - 750.

the register EPwm3Regs.TBPHS.half.TBPHS presents a constant value of 40. the register EPwm4Regs.TBPHS.half.TBPHS is adjusted in real-time as a function of

(*ePWM[4]).TBPRD in the range between 64 - 155 (TBPHS isa directly proportional to TBPRD)."


As I explained earlier - issue is not in the module configuration. It's perfectly valid configuration. But the runtime updates you are doing to the TBPRD/TBPHS values might result in this condition. 

- When you choose shadow ((*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW;) loading of new value into the TBPRD happens at the next counter zero. 
- I believe, You are running in to a boundary condition where the new TBPRD value is not loaded in to EPWM4, because counter zero did not occur for EPWM4 due to phase loading. That's the reason I asked you to disable the phase loading and check the behavior and your results confirm the same.
- So you need to make sure the value of phase being loaded, status of the EPWM4 time base counter etc are proper and counter would proceed to zero and new TBPRD value takes effect.
- If the Counter of EPWM4 never reaches to zero - new period value will not be loaded and the counter may continue to keep counting and no PWM output will be generated during those cycles.

-Bharathi.

Dear Bharathi,

Thanks for your patience.

- So you need to make sure the value of phase being loaded, status of the EPWM4 time base counter etc are proper and counter would proceed to zero and new TBPRD value takes effect.

I don't know exactly how to make sure that the value of phase being loaded, status of the EPWM4 time base counter etc are proper.
I thought that loading with a value of TBPHS < TBPRD would be enough to guarantee that time base counter always reaches zero at every switching period.

The action of disabling PHASE LOADING WHEN TZFRC IS ACTIVATED and ENABLING PHASE LOADING WHEN TZFRC IS CLEARED results in correct operation even with shadow mode enabled for EPWM4, but as Immediate mode shown to be less sensitive, for this problem, i will keep immediate load for TBPRD of EPWM4.

Please let me know if you have any other suggestion. 

//TBPRD LOADING

(*ePWM[1]).TBCTL.bit.PRDLD = TB_SHADOW;
(*ePWM[2]).TBCTL.bit.PRDLD = TB_SHADOW;
(*ePWM[3]).TBCTL.bit.PRDLD = TB_SHADOW;
(*ePWM[4]).TBCTL.bit.PRDLD = TB_IMMEDIATE;

//EPWM3 TRIPZONE AND PHSEN CONFIGURATION
//DISABLE PHASE LOADING WHEN TZFRC IS ACTIVATED
EALLOW;
EPwm3Regs.TZFRC.bit.OST=1;
EDIS;
EPwm3Regs.TBCTL.bit.PHSEN=0;

//ENABLE PHASE LOADING WHEN TZFRC IS CLEARED
EPwm3Regs.TBCTL.bit.PHSEN=1;
EALLOW;
EPwm3Regs.TZFRC.bit.CBC=1;
EPwm3Regs.TZCLR.bit.OST=1;
EDIS;

//EPWM4 TRIPZONE AND PHSEN CONFIGURATION

//DISABLE PHASE LOADING WHEN TZFRC IS ACTIVATED
EALLOW;
EPwm4Regs.TZFRC.bit.OST=1;
EDIS;
EPwm4Regs.DBRED = 750;
EPwm4Regs.DBFED = 750;
EPwm4Regs.TBCTL.bit.PHSEN = 0;

//ENABLE PHASE LOADING WHEN TZFRC IS CLEARED
EALLOW;
EPwm4Regs.TZCLR.bit.OST=1;
EDIS;
EPwm4Regs.TBCTL.bit.PHSEN=1;

Best Regards,
Ricardo

Ricardo,

Like I said earlier - it depends on your overall software and when you are making updates to PRD/PHS w.r.t. the epwm time base counter status.
Module configuration is fine.
You can try this - Since you are using up count mode, take interrupt on counter zero of epwm1 (whichever is the first in the sync chain) and update PRD/PHS of all EPWMs in time before any counters reach zero. That way the new value of PRD will take effect for all PWMs.
This is easy to figure out from calculation - value of the phase you are loading into, say PWM4, and cycles remaining before it hits zero i.e. (previous value of PRD - current phase loaded). Hope it is clear. Making a diagram of various events and instances of loading new values, for your software, would help you visualize the problem and solution.
I would not suggest using Immediate mode - as it doesn't rule out the occurrence of the problem.

-Bharathi.

Dear Barathi,

I observed a relation between the way PWM is started after a TZFRC and the wrong behavior of EPWM4 operating with PHSEN enabled in shadow mode.

I would like to receive your comments about the tests shown below.

Case 1) Problem with epwm4 after TZCLR.bit.OST

(*ePWM[4]).TBCTL.bit.PHSEN = TB_ENABLE;

(*ePWM[4]).TBCTL.bit.PRDLD = TB_SHADOW;

EPwm4Regs.TBPHS.half.TBPHS = 1

I set a fixed and small value (1) for EPWM4 TBPHS ;

I remove the code where TBPHS was being updated in real time.

my routine to stop EPWM4

   EALLOW;

   EPwm4Regs.TZFRC.bit.OST=1; // Habilita shutdown

   EDIS;  

my routine to start EPWM4

           EALLOW;

        EPwm4Regs.TZCLR.bit.OST=1; // LIMPA FLAG TZCLR

     EDIS;

my routine to stop EPWM4

   EALLOW;

   EPwm4Regs.TZFRC.bit.OST=1; // Habilita shutdown

   EDIS;  

FIGURE LEGEND:

YELLOW - EPWMSYNCO

CYAN - THE LOW STATE IS THE PERIOD WHERE THE REAL TIME CALCULATIONS AND PWM UPDATES HAPPENS

GREEN - EPWM3B (ACTIVE LOW)

MAGENTA - EPWM4B (ACTIVE HIGH)

Case 2) The problem does not happen in this case.

I changed the start routine 

first i set TZFRC.bit.CBC and after that i clear TZCLR.bit.OST

my new routine to start EPWM4

       EALLOW;

       EPwm4Regs.TZFRC.bit.CBC=1;

        EPwm4Regs.TZCLR.bit.OST=1; // LIMPA FLAG TZCLR

     EDIS;

FIGURE LEGEND:

YELLOW - EPWMSYNCO

CYAN - THE LOW STATE IS THE PERIOD WHERE THE REAL TIME CALCULATIONS AND PWM UPDATES HAPPENS

GREEN - EPWM3B (ACTIVE LOW)

MAGENTA - EPWM4B (ACTIVE HIGH)

Hi Ricardo,

i think this is expected behavior.
In case 2 where you are forcing CBC event - the clear of CBC event would result in PWM being resumed at next counter zero. This would also mean that new period and phase value would be loaded into the counter as expected.
In case 1 when you are forcing OST event - when you clear the trip action the PWM would resume operation immediately - not waiting for a counter zero event. This could possibly result in erroneous behavior depending on when in s/w w.r.t. PWM state you are clearing the flags.

-Bharathi.