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During multiprocessor operation, when the device has been specifically addressed, the SLEEP bit will have been disabled via software and the interrupts for received data will be coming. Due to this state of operation, the SLEEP bit by itself is not an accurate designation of a new frame. In order to know when the data ends and the next address/frame will begin, the RXWAKE should be read when the rx interrupt occurs. When RXWAKE is '1', it means that either an idle period has occured or the address bit has been set, designating a new 'frame' in either Idle-line or Address-bit modes respectively. For this new frame, the address bit should be checked against the 'self' designated address to see if the data in the new frame should be read or if the SLEEP bit can be set.
I don't believe we have any specific example code for this mode of operation, but I'll try to explain a bit more: A read of RXWAKE in your rx isr will tell you if a new frame has occured. If RXWAKE is '1', the sleep mode processing should occur (set/keep sleep at '1' if address does not apply, set sleep to '0' if address does apply). If RXWAKE is '0' and you still get the interrupt, then you have theoretically already been through the sleep processing, and now you are getting interrupted on actual data. Data should be read and processed accoringly. When RXWAKE is '1' again going into your isr, then an idle period or an address bit has been detected, and a new frame is beginning.