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Chip Select Not Being Set High Consistently During Read or Write Operations

Stephen V
Prodigy 145 points


I am trying to write to an external 1553 chip connected to XINTF Zone 6 on my F28335 MCU. When I look at the write (or read) transactions on a logic analyzer, I do not see the Chip Select line transition high in between my writes to the device consistently. My code is just writing sequentially to different registers of a struct which is mapped to the XINTF memory region (No DMA).

Below is the settings for the XINTF:

  XintfRegs.XTIMING6.bit.X2TIMING = 1;

  XintfRegs.XTIMING6.bit.XSIZE = 3;

  XintfRegs.XTIMING6.bit.READYMODE = 1;

  XintfRegs.XTIMING6.bit.USEREADY = 1;

  XintfRegs.XTIMING6.bit.XRDLEAD = 1;   

  XintfRegs.XTIMING6.bit.XRDACTIVE = 2;

  XintfRegs.XTIMING6.bit.XRDTRAIL = 3; 

  XintfRegs.XTIMING6.bit.XWRLEAD = 1;

  XintfRegs.XTIMING6.bit.XWRACTIVE = 1;

  XintfRegs.XTIMING6.bit.XWRTRAIL = 3;

 

I've included a screenshot from the Logic Analyzer which you can see the missing toggles on the fourth line "RT_1553_CS_N".  Let me know if anymore information is required to help solve this problem.  Thank you.

 

  • 0
    TI__Guru* 92200 points

    Stephen V said:
    I am trying to write to an external 1553 chip connected to XINTF Zone 6 on my F28335 MCU. When I look at the write (or read) transactions on a logic analyzer, I do not see the Chip Select line transition high in between my writes to the device consistently. My code is just writing sequentially to different registers of a struct which is mapped to the XINTF memory region (No DMA).

    Stephen

    Please see if this Wiki FAQ answers your question:

    http://processors.wiki.ti.com/index.php/External_Interface_XINTF_Type_1_FAQ_for_C2000#Q:_Will_the_chip_select_line_stay_low_during_back-to-back_accesses_to_the_same_zone.3F

     

     

  • 0 in reply to Lori Heustess
    Prodigy 145 points

    I don't think we have any way of enforcing the active phase to end on the falling edge of the XCLKOUT since we are sampling the XREADY signal (and therefore the external device controls when the active phase ends). Is that the only way we can ensure that the chip select is brought high between transactions? 

  • 0 in reply to Stephen V
    TI__Guru* 92200 points

    Stephen V said:
    I don't think we have any way of enforcing the active phase to end on the falling edge of the XCLKOUT since we are sampling the XREADY signal (and therefore the external device controls when the active phase ends). Is that the only way we can ensure that the chip select is brought high between transactions? 

    Stephen,

    Yes, that's the only way to control it through hardware.  Otherwise it will stay low if the accesses come back to back.  Another possibility I can think of, but is not elegant, is to always have some sort of delay in software between accesses.  Also make sure the write buffer is disabled so you can't fill it up - instead the CPU will be stalled while the write takes place.

    Regards,

    -Lori