F28335 ADC Wont Convert Unless the ADC Interrupt is Enabled

Edward Sanders

Greetings,

I have an application where I am using the ADC to do conversions which are DMAd into memory. At the end of the conversions, the DMA gives me an interrupt which tells me that the process is complete and all data are in the memory.

But I have found that in order to have the ADC do any conversions, I need to have the ADC interrupt enabled, even though I don’t need it. Should I need to do this? The initialization code is as follows:

#define ADC_MODCLK 0x3

#define ADC_ADCBGRFND 0x00C0

#define ADC_ADCPWDN 0x0020

#define ADCTRL3_INIT ADC_ADCBGRFND + ADC_ADCPWDN

#define ADCMAXCONV_INIT 15 // 16 conversions

#define ADCCHSELSEQ_SETUP 0x0000 // All are channel 0.

void AdcHwInit()

{

InitAdc();

EALLOW;

SysCtrlRegs.HISPCP.all = ADC_MODCLK;

// PieVectTable.ADCINT = &AdcInterrupt;

EDIS;

AdcRegs.ADCTRL1.bit.ACQ_PS = 0;

AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;

AdcRegs.ADCTRL1.bit.CONT_RUN = 1;

AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ = 1;

AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0;

AdcRegs.ADCTRL3.all = ADCTRL3_INIT;

AdcRegs.ADCMAXCONV.all = ADCMAXCONV_INIT;

}

When we start the conversions, we execute the following code:

void AdcSetupCapture()

{

AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;

AdcRegs.ADCCHSELSEQ1.all = ADCCHSELSEQ_SETUP;

AdcRegs.ADCCHSELSEQ2.all = ADCCHSELSEQ_SETUP;

AdcRegs.ADCCHSELSEQ3.all = ADCCHSELSEQ_SETUP;

AdcRegs.ADCCHSELSEQ4.all = ADCCHSELSEQ_SETUP;

}

And the interrupt:

void AdcInterrupt()

{

AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}

If I enable the interrupt routine in AdcHwInit, and change AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 to be initialized to 1, I will receive the conversions. Alternatively, If I simply enable the interrupt routine, I will end up at ADCINT_ISR with all the conversions too. So the appearance is that the ADC interrupt must be enabled for conversions to occur. I’m obviously missing something. Any help would be appreciated.

Thank you,

over 9 years ago

0 Whitney Dewey over 9 years ago

TI__Guru 53835 points

Ed,

Are the conversions not happening or are they happening but the DMA just isn't getting triggered? If it's the latter, I suspect INT_ENA_SEQ1 needs to be set to allow the interrupt signal to reach the DMA and trigger the transfer. Does that seem to accurately describe the behavior you're seeing?

Whitney

0 Edward Sanders over 9 years ago in reply to Whitney Dewey

Intellectual 430 points

Hi Whitney,

That sounds very plausible. I have copied the register values at the time of the failure. If I’m interpreting them correctly, it seems to indicate that a few conversions occurred, but nothing was sent to the DMA. Is this correct?

Thank you,

ADC ADC Registers

ADCTRL1 0x0050 ADC Control Register 1 [Memory Mapped]

ADCTRL2 0xA000 ADC Control Register 2 [Memory Mapped]

ADCMAXCONV 0x000F ADC Maximum Conversion Channels Register [Memory Mapped]

ADCCHSELSEQ1 0x0000 ADC Channel Select Sequencing Control Register 1 [Memory Mapped]

ADCCHSELSEQ2 0x0000 ADC Channel Select Sequencing Control Register 2 [Memory Mapped]

ADCCHSELSEQ3 0x0000 ADC Channel Select Sequencing Control Register 3 [Memory Mapped]

ADCCHSELSEQ4 0x0000 ADC Channel Select Sequencing Control Register 4 [Memory Mapped]

ADCASEQSR 0x0A06 ADC Auto-Sequence Status Register [Memory Mapped]

ADCRESULT0 0x0010 ADC Conversion Result Buffer Register 0 [Memory Mapped]

ADCRESULT1 0x0000 ADC Conversion Result Buffer Register 1 [Memory Mapped]

ADCRESULT2 0x0000 ADC Conversion Result Buffer Register 2 [Memory Mapped]

ADCRESULT3 0x0000 ADC Conversion Result Buffer Register 3 [Memory Mapped]

ADCRESULT4 0x0000 ADC Conversion Result Buffer Register 4 [Memory Mapped]

ADCRESULT5 0x0000 ADC Conversion Result Buffer Register 5 [Memory Mapped]

ADCRESULT6 0x0000 ADC Conversion Result Buffer Register 6 [Memory Mapped]

ADCRESULT7 0x0000 ADC Conversion Result Buffer Register 7 [Memory Mapped]

ADCRESULT8 0x0000 ADC Conversion Result Buffer Register 8 [Memory Mapped]

ADCRESULT9 0x0000 ADC Conversion Result Buffer Register 9 [Memory Mapped]

ADCRESULT10 0x0010 ADC Conversion Result Buffer Register 10 [Memory Mapped]

ADCRESULT11 0x0000 ADC Conversion Result Buffer Register 11 [Memory Mapped]

ADCRESULT12 0x0010 ADC Conversion Result Buffer Register 12 [Memory Mapped]

ADCRESULT13 0x0010 ADC Conversion Result Buffer Register 13 [Memory Mapped]

ADCRESULT14 0x0000 ADC Conversion Result Buffer Register 14 [Memory Mapped]

ADCRESULT15 0x0000 ADC Conversion Result Buffer Register 15 [Memory Mapped]

ADCTRL3 0x00E0 ADC Control Register 3 [Memory Mapped]

ADCST 0x0005 ADC Status Register [Memory Mapped]

ADCREFSEL 0x1F28 ADC Reference Select Register [Memory Mapped]

ADCOFFTRIM 0x01F7 ADC Offset Trim Register [Memory Mapped]

ADCMIRROR ADC Mirror Registers

ADCRESULT_MIRROR_0 0x0000 ADC Conversion Result Buffer Register 0 Mirror [Memory Mapped]

ADCRESULT_MIRROR_1 0x0000 ADC Conversion Result Buffer Register 1 Mirror [Memory Mapped]

ADCRESULT_MIRROR_2 0x0002 ADC Conversion Result Buffer Register 2 Mirror [Memory Mapped]

ADCRESULT_MIRROR_3 0x0001 ADC Conversion Result Buffer Register 3 Mirror [Memory Mapped]

ADCRESULT_MIRROR_4 0x0000 ADC Conversion Result Buffer Register 4 Mirror [Memory Mapped]

ADCRESULT_MIRROR_5 0x0000 ADC Conversion Result Buffer Register 5 Mirror [Memory Mapped]

ADCRESULT_MIRROR_6 0x0000 ADC Conversion Result Buffer Register 6 Mirror [Memory Mapped]

ADCRESULT_MIRROR_7 0x0000 ADC Conversion Result Buffer Register 7 Mirror [Memory Mapped]

ADCRESULT_MIRROR_8 0x0000 ADC Conversion Result Buffer Register 8 Mirror [Memory Mapped]

ADCRESULT_MIRROR_9 0x0000 ADC Conversion Result Buffer Register 9 Mirror [Memory Mapped]

ADCRESULT_MIRROR_10 0x0000 ADC Conversion Result Buffer Register 10 Mirror [Memory Mapped]

ADCRESULT_MIRROR_11 0x0000 ADC Conversion Result Buffer Register 11 Mirror [Memory Mapped]

ADCRESULT_MIRROR_12 0x0000 ADC Conversion Result Buffer Register 12 Mirror [Memory Mapped]

ADCRESULT_MIRROR_13 0x0001 ADC Conversion Result Buffer Register 13 Mirror [Memory Mapped]

ADCRESULT_MIRROR_14 0x0001 ADC Conversion Result Buffer Register 14 Mirror [Memory Mapped]

ADCRESULT_MIRROR_15 0x0000 ADC Conversion Result Buffer Register 15 Mirror [Memory Mapped]

DMA DMA Registers

[0 ... 99]

DMACTRL 0x0000 DMA Control Register [Memory Mapped]

DEBUGCTRL 0x8000 Debug Control Register [Memory Mapped]

REVISION 0x0000 Peripheral Revision Register [Memory Mapped]

PRIORITYCTRL1 0x0000 Priority Control Register 1 [Memory Mapped]

PRIORITYSTAT 0x0000 Priority Status Register [Memory Mapped]

DMACH1_MODE 0x8301 DMA Channel 1 Mode Register [Memory Mapped]

DMACH1_CONTROL 0x2000 DMA Channel 1 Control Register [Memory Mapped]

DMACH1_BURST_SIZE 0x000F DMA Channel 1 Burst Size Register [Memory Mapped]

DMACH1_BURST_COUNT 0x0000 DMA Channel 1 Burst Count Register [Memory Mapped]

DMACH1_SRC_BURST_STEP 0x0001 DMA Channel 1 Source Burst Step Size Register [Memory Mapped]

DMACH1_DST_BURST_STEP 0x0001 DMA Channel 1 Destination Burst Step Size Register [Memory Mapped]

DMACH1_TRANSFER_SIZE 0x007F DMA Channel 1 Transfer Size Register [Memory Mapped]

DMACH1_TRANSFER_COUNT 0x0000 DMA Channel 1 Transfer Count Register [Memory Mapped]

DMACH1_SRC_TRANSFER_STEP 0x0001 DMA Channel 1 Source Transfer Step Size Register [Memory Mapped]

DMACH1_DST_TRANSFER_STEP 0x0010 DMA Channel 1 Destination Transfer Step Size Register [Memory Mapped]

DMACH1_SRC_WRAP_SIZE 0x0000 DMA Channel 1 Source Wrap Size Register [Memory Mapped]

DMACH1_SRC_WRAP_COUNT 0x0000 DMA Channel 1 Source Wrap Count Register [Memory Mapped]

DMACH1_SRC_WRAP_STEP 0x0000 DMA Channel 1 Source Wrap Step Size Register [Memory Mapped]

DMACH1_DST_WRAP_SIZE 0x0000 DMA Channel 1 Destination Wrap Size Register [Memory Mapped]

DMACH1_DST_WRAP_COUNT 0x0000 DMA Channel 1 Destination Wrap Count Register [Memory Mapped]

DMACH1_DST_WRAP_STEP 0x0010 DMA Channel 1 Destination Wrap Step Size Register [Memory Mapped]

DMACH1_SRC_BEG_ADDR_SHADOW 0x00000B00 DMA Channel 1 Shadow Source Begin Register [Memory Mapped]

DMACH1_SRC_ADDR_SHADOW 0x00000B00 DMA Channel 1 Shadow Source Current Address Register [Memory Mapped]

DMACH1_SRC_BEG_ADDR_ACTIVE 0x00000000 DMA Channel 1 Active Source Begin Register [Memory Mapped]

DMACH1_SRC_ADDR_ACTIVE 0x00000000 DMA Channel 1 Active Source Current Address Register [Memory Mapped]

DMACH1_DST_BEG_ADDR_SHADOW 0x0000C800 DMA Channel 1 Shadow Destination Begin Register [Memory Mapped]

DMACH1_DST_ADDR_SHADOW 0x0000C800 DMA Channel 1 Shadow Destination Current Address Register [Memory Mapped]

DMACH1_DST_BEG_ADDR_ACTIVE 0x00000000 DMA Channel 1 Active Destination Begin Register [Memory Mapped]

DMACH1_DST_ADDR_ACTIVE 0x00000000 DMA Channel 1 Active Destination Current Address Register [Memory Mapped]

0 Whitney Dewey over 9 years ago in reply to Edward Sanders

TI__Guru 53835 points

Ed,

I can see that the INT_SEQ1 flag is set, but the DMA is still waiting to be triggered (RUNSTS is still 1), so I think that is correct.

Whitney

0 Edward Sanders over 9 years ago in reply to Whitney Dewey

Intellectual 430 points

Whitney,

Sounds like we are on the right track! To fix it, should I change the initialization of the CONTINUOUS bit to 1? I’ve tried that, but it always reads back as a 0. In short, what do I need to do to fix it?

Thanks,

0 Whitney Dewey over 9 years ago in reply to Edward Sanders

TI__Guru 53835 points

Hi Ed,

Are you still having issues after setting INT_ENA_SEQ1 to 1? If you don't want the actual interrupt to occur, keep it disabled in the PIE (PIEIER1.INTx1 = 0). Was that the main concern or was there another issue?

Whitney

0 Edward Sanders over 9 years ago in reply to Whitney Dewey

Intellectual 430 points

Hi Whitney,

Yes, I am still having the issue. I tried your suggestion and placed the instruction between the EALLOW and EDIS, but I still receive the interrupt. Is there something else I need to add?

Thank you,

0 Edward Sanders over 9 years ago in reply to Edward Sanders

Intellectual 430 points

Hi Whitney,

And of course, immediately after I posted that, I figured out how to get rid of it. I disabled the INTx6 interrupt. Does that make sense to you?

Thank you,

0 Whitney Dewey over 9 years ago in reply to Edward Sanders

TI__Guru 53835 points

Yes, that does make sense. I made an incorrect assumption about which interrupt you were using. Sorry for the confusion.

Whitney

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F28335 ADC Wont Convert Unless the ADC Interrupt is Enabled