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F28335 DMA and ADC configuation issue

ALABN ALBAN
Prodigy 30 points

Good morning,

I have an issue with the ADC and DMA configuration and it seems i am not the only one to get issue with the DMA& ADC configuration.

I want to oversample one input using 8 adc inputs, and fill one outputbuffer of 2048 points.

Based on my following configuration, i still observe some missing point in my buffer.

I am not sure i am initializing correctly the DMA..but i don t see where would be the error.

Does any one see any initialization issue?

Regards

HEre is the ADC configuration i use:

// ADC configuration

AdcRegs.ADCTRL3.all = 0x00E0u;
DELAY_US(ADC_usDELAY);
AdcRegs.ADCTRL1.bit.SUSMOD = 3u;
AdcRegs.ADCTRL1.bit.CPS =0u;
AdcRegs.ADCTRL1.bit.ACQ_PS = 0;
AdcRegs.ADCTRL3.bit.ADCCLKPS = 0x1;

AdcRegs.ADCTRL1.bit.SEQ_OVRD =1;

AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;
ADC_START_CONT_RUN;//1; // Continuous mode
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 0x1;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 0x1;

AdcRegs.ADCMAXCONV.bit.MAX_CONV1 =8-1;
AdcRegs.ADCCHSELSEQ1.bit.CONV00=0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV01=0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV02=0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV03=0x0;
AdcRegs.ADCCHSELSEQ2.bit.CONV04=0x0;
AdcRegs.ADCCHSELSEQ2.bit.CONV05=0x0;
AdcRegs.ADCCHSELSEQ2.bit.CONV06=0x0;
AdcRegs.ADCCHSELSEQ2.bit.CONV07=0x0;

// DMA configuration

DMAInitialize();
DMADestA = (Uint16*) Output; //Point DMA destination to the beginning of the array

DMASourceA = &AdcMirror.ADCRESULT0;

DMACH1AddrConfig(DMADestA,DMASourceA);

DMACH1BurstConfig(8-1,1,1); // 8 word by burst
DMACH1TransferConfig(256-1,1,1); ;// 2048/8 burst transfer required
DMACH1WrapConfig (1,0,2048,0);//

DMACH1ModeConfig(DMA_SEQ1INT,PERINT_ENABLE,ONESHOT_DISABLE,CONT_DISABLE,SYNC_DISABLE,SYNC_SRC,
OVERFLOW_DISABLE,SIXTEEN_BIT,CHINT_END,CHINT_ENABLE);

  • 0
    TI__Guru** 116081 points

    Hi,

    I don't see anything wrong with DMA configuration. Could you attach the data you receiving and the expected data (only data for 3 burst transfer).

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 30 points
    Well , wheni acquire a pure square signal at a frequency of 10 KHZ for instance, i observe that there are bad sampled. (16 samples are periodically wrong).
    I guess i am not very confident with the TI API to configure the DMA.
    Indeed normally after each the 8 ADC register transfer, i should wrap the source adress by offset of -8. Since the burst will have increase the adress of the source by 8 (8 adc registers).
    So for the DMACH1TransferConfig API , i am not confident with the 2nd and thrid parameter . Should it be DMACH1TransferConfig(256-1,1,1) or DMACH1TransferConfig(256-1,0,1)?

    At last for the WRAP configuration, for the source adress it should wrap every 8 adress increase (since the initial burst increased the adress by 8) and the destiantion adress should wrap by an offsrt of -2048 adress since.
    SO i dont know if i should use DMACH1WrapConfig (1,0,2048,0) or DMACH1WrapConfig (0,-8,0,-2048).

    I dont find clear example in fact.


    Regards
  • 0 in reply to ALABN ALBAN
    TI__Guru** 116081 points

    Hi,

    So for the DMACH1TransferConfig API , i am not confident with the 2nd and thrid parameter . Should it be DMACH1TransferConfig(256-1,1,1) or DMACH1TransferConfig(256-1,0,1)?

    Source step in this case should not matter because it's ignored when wrap happens.

    At last for the WRAP configuration, for the source adress it should wrap every 8 adress increase (since the initial burst increased the adress by 8) and the destiantion adress should wrap by an offsrt of -2048 adress since.

    I was under impression that you are planning to wrap after 2 burst because ADC has 16 result registers. But if it's only for 8 then you need to correct ..WrapConfig function call. Since there is no wrap for destination, you should have DST_WRAP_SIZE as 0xFFFF.

    DMACH1WrapConfig (0,0,0xFFFF,0).

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 116081 points
    Hi,
    Did it work ? Let us know if you have further queries on this?

    Regards,
    Vivek Singh
  • 0 in reply to Vivek Singh
    Prodigy 30 points

    Hello,

    In fact it seems to work but in limited sampling rate range.

    I am using a 30 Mhz clock ; and NO PLL.

    And i observe that it works up to 5 MSPS.

    But for any sampling rate greater than 5 MSPS; it fails.

    For instance it fails at 6 MSPS or 7.5MSPS where there are missing point.

    It seems to come from the ADC limitations .

    regards

  • 0 in reply to ALABN ALBAN
    TI__Guru 60865 points
    Hi Alban,

    If the device is running at 30MHz and the maximum ADCCLK is 25MHz, then I think you have to set the ADCCLK to 15MHz based on available clock dividers? This will give you a maximum sample rate of (15MHz / 25 MHz) * 12.5 MSPS = 7.5MSPS.