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ePWM Timer Interrupt F28069M

Other Parts Discussed in Thread: CONTROLSUITE

 Hello, 

I am a newbie for Piccolo F28069. Now, I am reading the example code for ePWM Timer Interrupt  in controlSUITE, but there are somes points in the example that I don't understand well

The discription for the codes 

//! This example configures the ePWM Timers and increments a counter each
//! time an interrupt is taken.
//! In this example:
//!  - All ePWM's are initialized.
//!  - All timers have the same period.
//!  - The timers are started sync'ed.
//!  - An interrupt is taken on a zero event for each ePWM timer.
//!  - ePWM1: takes an interrupt every event.
//!  - ePWM2: takes an interrupt every 2nd event.
//!  - ePWM3: takes an interrupt every 3rd event.
//!  - ePWM4: takes an interrupt every event. 
//! Thus the Interrupt count for ePWM1 and ePWM4 should be equal.The 
//! interrupt count for ePWM2 should be about half that of ePWM1 and 
//! the interrupt count for ePWM3 should be about 1/3 that of ePWM1.

And the probleme is here 

EPwm1Regs.TBPHS.half.TBPHS = 100;
EPwm2Regs.TBPHS.half.TBPHS = 200;
EPwm3Regs.TBPHS.half.TBPHS = 300;
EPwm4Regs.TBPHS.half.TBPHS = 400;

EPwm1Regs.TBPRD = PWM1_TIMER_TBPRD;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;    // Count up
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = PWM1_INT_ENABLE;  // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;   

So the question is:

1. Why they set different value of TBPHS.half.TBPHS  for each epwm, and TBPHS.half.TBPHS means ?

2. If I want to take an interrupt every 4th event, I will change "EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;" to "EPwm1Regs.ETPS.bit.INTPRD = ET_4TH;"  ?

3. I see that there is another example for CPU Timer, so there is diference between CPU TImer and ePWM Timer ?. If I dont make a mistake, CPU Timer 0 generates ePWM, but CPU Timer 1  and 2 for another purposes.

Thanks for all your help

Max

  • Hello Maxime,

    1. Why they set different value of TBPHS.half.TBPHS  for each epwm, and TBPHS.half.TBPHS means ?

     - The author of this example inserted a phase offset between the four time-bases, presumably to make the 'scope traces look more interesting.  The TBPHS register is actually 32-bits in length: the upper 16 bits control coarse offset measured in TBCLK increments, the lower 16 bits a high resolution mode.  Defining the register in this way allows each part to be written independently of the other, if that's what the user wants to do.  It's instructive to look at the definition in lines 399-407 of the "F2806x_EPwm.h" header file. 

    2. If I want to take an interrupt every 4th event, I will change "EPwm1Regs.ETPS.bit.INTPRD = ET_1ST;" to "EPwm1Regs.ETPS.bit.INTPRD = ET_4TH;"  ?

     - That isn't an option in the ET module, unfortunately.  You can take an interrupt every event, every second event, or every third event.  If you want to divide further you'll need to do it inside your ISR.  The definitions used are in lines 149-152 of the header file "F2806x_EPwm_defines.h", and on page 366 of the User's Guide (spruh18e.pdf).

    3. I see that there is another example for CPU Timer, so there is diference between CPU TImer and ePWM Timer ?. If I dont make a mistake, CPU Timer 0 generates ePWM, but CPU Timer 1  and 2 for another purposes.

     - The three CPU timers have a different architecture from the EPwm timers.  They are intended for general purpose use by user software.  If you are using TI-RTOS I believe timers 0 and 1 are reserved, otherwise all are available to the user.  None of the CPU timers can generate PWM.

    Regards,

    Richard