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EMIF1 arbitration of TMS320F28377D

vesgine
Expert 1315 points

EMIF1 is shared between CPU1 and CPU2. In the default, CPU1 is the master for EMIF1. Now CPU2 wants to access EMIF1, is the following steps right?

1. CPU2 writes the value of 0x93A5CE7 to the KEY filed of EMIF1MSEL register. This is used to allowing to change the MSEL_EMIF1 bits.

2. CPU2 writes the value of 0x10 to the MSEL_EMIF1 field of EMIF1MSEL register. This is used to grab the master ownership for CPU2.

3. CPU2 accesses EMIF1.

After CPU2 completing access of EMIF1, when will the CPU1 grab the master ownership again? Does the CPU1 need to execute the above steps to grab the master ownership?

Another question is that if one CPU tries to access the EMIF1 while the other CPU is accessing EMIF1 in progress, will the first CPU halt and wait until the second CPU release the ownership?

  • 0
    TI__Guru** 115281 points

    Hi,

    1. CPU2 writes the value of 0x93A5CE7 to the KEY filed of EMIF1MSEL register. This is used to allowing to change the MSEL_EMIF1 bits.

    2. CPU2 writes the value of 0x10 to the MSEL_EMIF1 field of EMIF1MSEL register. This is used to grab the master ownership for CPU2.

    This is correct but step 1 and step 2 need to be perform at same time. Both values need to be written together (value 0x93A5CE72). Also the value for MSEL_EMIF1 is "10" not "0x10".

    After CPU2 completing access of EMIF1, when will the CPU1 grab the master ownership again? Does the CPU1 need to execute the above steps to grab the master ownership?

    After CPU2 is done with EMIF access, it need to release the semaphore by writing the value 00 into MSEL_EMIF1 field along with KEY value. After that only CPU1 can grab the semaphore again(or since 00 is default value which is for EMIF1, it need not to grab).

    Another question is that if one CPU tries to access the EMIF1 while the other CPU is accessing EMIF1 in progress, will the first CPU halt and wait until the second CPU release the ownership?

    Read are allowed in this case. So other CPU will get the correct values. Writes will be ignored.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1315 points
    Hi, Vivek

    Assuming CPU1 tries to write EMIF1 while CPU2 is already accessing EMIF1 in the meantime, the write operation of CPU1 will be ignored. Is there any prompt message indicating that activity? If not, how does the user know that write operation of CPU1 failed?
  • 0 in reply to vesgine
    TI__Guru** 115281 points

    Hi,

    In case of such violation, an interrupt will be generated on interrupt line "RAM_ACCESS_VIOLATION" (INT12.12) and the address for which violation happened will be latched into one of registers in "ACCESS_PROTECTION_REGS" (depending on master violation or non-master violation).

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Guru** 115281 points
    Let us know if you have any further queries on this.

    Regards,
    Vivek Singh
  • 0 in reply to Vivek Singh
    Expert 1315 points

    So the write operation still failed anyway when such violation occurred and the user has to try to re-execute the write operation. In this case, only the address is latched but the data is not latched, then how to re-execute the write operation? 

    Is there any way to assure the success of write operation with and without violation? e.g. polling some flags.

  • 0 in reply to vesgine
    TI__Guru** 115281 points

    Hi,

    That's correct. Only address is latched and not data. Address is latched for diagnosis.  By the time interrupt will happen there may be multiple write which were blocked. In this case user need to correct the issues and re-run the routine for which the writes were blocked.

    Is there any way to assure the success of write operation with and without violation? e.g. polling some flags.

    Not sure if I follow the question. In case of violation, writes will be always blocked and write data is lost.

    In this case why data is getting written to memory block which is protected?

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Expert 1315 points

    Hi,

    My second question is that,  is there any way to avoid write violation by polling some flags or other methods from the user's perspective?

  • 0 in reply to vesgine
    TI__Guru** 115281 points
    Hi,

    Yes, in code before doing write, check the semaphore value to know which CPU has master ownership for the EMIF and if ownership is not with the CPU, running the code then Ist grab the ownership and then perform the write operation.

    Regards,
    Vivek Singh