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what would be the EnDat/BiSS polling rate on TMS320F28379D?

Seungryul Moon
Prodigy 80 points

Other Parts Discussed in Thread: TMS320F28379D, CONTROLSUITE

Hi,

My name is Seung Moon from Virginia Tech.

I am planning on implementing either EnDat or BiSS interface with TMS320F28379D.

What if I would dedicate either the main core or CLA to poll the encoder position, what would be the maximum sampling rate?

To clarify the question, I am going to present an example.

Let's say, I am going to drive a three-phase PMSM using TMS320F28379D. The switching frequency is 20 kHz, and I am sampling the position and motor current synchronously at 20 kHz. Will the EnDat/BiSS  be able to give the DSP the position at the rate of 20 kHz? Can I sample the position at 100 kHz?? 200 kHz?? What would be the maximum sampling rate for position feedback from EnDat/BiSS?

The same question can be rephrase to this. What is the latency of the EnDat/BiSS from the position request command to final value calculation?

This is what I have so far using EnDat.

200MHz system clock for TMS320F28379D. EnDat clock is limited to maximum of sysclock/24 ~= 8MHz. 

For every interrupt cycle, I would need to run following command.

(from sprui35.pdf )

PM_endat22_setupCommand (1160 cycles)

PM_endat22_startOperation (46 cycles)

PM_endat22_getCrcPos (220 cycles)

PM_endat22_receiveData (500 cycles)

Total of about 2000 cycles. So 200MHz / 2000 = 100 kHz. Therefore, is the maximum position sampling rate about 100 kHz?

I am asking the question without rigorously reading the paper, so I am sure I am wrong on many things.

Thanks for reading and taking your time to answer.

Seung Moon

  • 0
    TI__Mastermind 24095 points

    Hi Seung Moon,

    Thanks for sharing your project details. I don't think you need to dedicate a CPU or CLA for this purpose.
    Position reading may well fit into rest of your control loop on the same CPU.
    You can refer to the example code for entire drive system here C:\ti\controlSUITE\development_kits\TMDSIDDK_v2.0
    Your understanding about the cycle behavior is correct. That should give you a pretty good idea of cycle time requirements.
    What is not explicitly mentioned is the time taken for actual transmission/communication between the encoder and 28379D on the physical layer.
    This would entirely depend on your system requirements i.e. the encoder being used, command being exercised, additional data enabled or disabled, clock freq. etc. During this time though, CPU can perform other tasks.

    -Bharathi.