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Sampling frequency

Githin George
Intellectual 290 points


Hi All,


How to Identify the sampling frequency of 28021 controller adc?

The cpu clock is of 60MHz. And the ADC trigger is done with ePWM which is of 150KHZ.

From the datasheet I got 333.33nSec as the total time of conversion for an ACQPS value of 6. So is this my sampling time or not?

  • 0
    Guru 192875 points
    Hi Githin,

    Sampling frequency would be equivalent to ePWM frequency.
    e2e.ti.com/.../336583

    What you seem to be concerned about is conversion time.

    Regards,
    Gautam
  • 0
    TI__Guru 60865 points
    Hi Githin,

    The sample rate is going to depend on how frequently you trigger the ADC (150kHz in your case), and how many conversions are processed for each trigger. If each of your triggers only causes one conversion, then the sample rate will be 150kSPS.

    There is also the sample-to-output latency. This will be the time between when the trigger is received to when the sample is ready. This will depend on the CPU frequency, the ADCCLK dividers, the S+H selection (ACQPS register setting), and if any other conversions are also triggered at the same time. I think for 60MHz ADCCLK, minimum S+H setting, and no other conversions triggered this will be around the 333 ns that you quote above.
  • 0 in reply to Devin Cottier
    Intellectual 290 points
    Thank You Devin,
    Correct me if I am wrong. So as you said if 150KHZ is my sampling frequency(arround 6.6uSec) and if the adc conversion time is 0.333uSec which means 6.3uSec my ADC is not doing anything.
    Can I do around 20 conversions (20x0.33=6uSec) by oversampling?
  • 0 in reply to Githin George
    TI__Guru 60865 points
    Githin,

    Yeah, this is essentially correct. I would encourage you to read the datasheet and TRM to understand exactly how the timings are calculated for different ADC settings.

    As far as oversampling, if you want to sample the same signal faster, then you would probably want to sync a second ePWM to the first, but running faster by some integer multiple to achieve this oversampling. This will ensure that the samples are evenly spaced. Alternately, you could trigger multiple SOCs with the 150kHz ePWM, and then just average these 4 or 8 at a time. The samples themselves would not be evenly spaced, but the averaged samples would be. You may also need to use the DMA to prevent the ADC ISR from using too much CPU bandwidth.

    Another thing you should consider are the device errata that pertain to the ADC. In particular, the first sample errata requires you to throw away the first sample in each set of conversions if you are running at 60MHz ADCCLK.