Other Parts Discussed in Thread: TMS320C28346
I am currently working with a Delfino F28377d dual core Control Card running at 192MHz on one core only. I noticed that there is a limitation with the ePwm modules with this part where the maximum speed is 100MHz. There is a clock division in the ClkCfg register that does a divide by 2 (96MHz) to make sure that it does not exceed the 100MHz specification. I have an application where I am running at a 4MHz (250ns) 12 count period (UP-Down TBCTR 96MHz / tick) and I am using the Hi Resolution MEP. The MEP has limitations as well where does it does not work within 3 ticks of 0 and the Period. I am also running it in synchronous mode with an Up-Down counter. So I am now exploring parts that are faster so that I can maximize resolution of the Pwm for our application without generating unwanted harmonics.
I have been looking at the TMS320C28346 because it has a 300MHz SYSCLKOUT that runs to the ePWM modules. There is no mention in the documentation of any limitation with the Pwm modules in the documentation. Does this part have the same limitation for the ePwm or can I run with a CLKDIV / 1 at a 300MHZ TBCLK tick rate? If so, it would allow for a SYSCLKOUT of 296MHz would give me a better ~55-60ps MEP resolution and also a 37 count Period. Can this be achieved with the TMS320C28346 or does the same limitation apply for this part as well?
John Allen
