TMS320F28377S ADC window comparator interrupts

Hi Devin,

OK Devin this is pretty much what i suspected after a quick look at the data sheets - many moons ago. Anyhow I  need to produce a circuit board and it seems to me that its gonna be too premature to try map the physical controller pins to the PCB since I am not sure how the CMPSS and XBAR is going to pan out thats why i intinially decided to do the comparator externally....haha

Can you possibly provide me with a sample project derrived from the  "cmpss_asynch" example project

showing how the XBAR is used to generate an interrupt from the CMPSS analog input. That would be really appreciated

Thanks

.

Nick,

Here's a copy of "cmpss_asynch" with some code snippets ported over from "external_interrupt" to enable GPIO interrupts using the comparator output pin.

//###########################################################################
// FILE:   cmpss_digital_filter_cpu01.c
// TITLE:  CMPSS Digital Filter Example Configuration for F2837xS.
//
//! \addtogroup cpu01_example_list
//! <h1> CMPSS Asynchronous Trip </h1>
//!
//! This example enables the CMPSS1 COMPH comparator and feeds the asynch
//! CTRIPOUTH to GPIO14/OUTPUTXBAR3 pin and CTRIPH to GPIO15/EPWM8B
//!
//! The COMPH inputs are:
//!   -  POS signal from CMPIN1P pin
//!   -  NEG signal from internal DACH
//!
//
//###########################################################################
// $TI Release: F2837xS Support Library v191 $
// $Release Date: Fri Mar 11 15:58:35 CST 2016 $
// $Copyright: Copyright (C) 2014-2016 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

#include "F28x_Project.h"     // Device Headerfile and Examples Include File

// Prototype statements for functions found within this file.
interrupt void xint1_isr(void);

// Global variables for this example
volatile Uint32 Xint1Count = 0;

//definitions for selecting DACH reference
#define REFERENCE_VDDA     0
#define REFERENCE_VDAC     1

//definitions for COMPH input selection
#define NEGIN_DAC          0
#define NEGIN_PIN          1

//definitions for CTRIPH/CTRIPOUTH output selection
#define CTRIP_ASYNCH       0
#define CTRIP_SYNCH        1
#define CTRIP_FILTER       2
#define CTRIP_LATCH        3

//definitions for selecting output pin
#define GPIO_CTRIP_PIN_NUM      14 //OUTPUTXBAR3 is mux'd with GPIO14
#define GPIO_CTRIP_PER_NUM       6 //OUTPUTXBAR3 is peripheral option 6 for GPIO14
#define GPIO_CTRIPOUT_PIN_NUM   15 //EPWM8B is mux'd with GPIO15
#define GPIO_CTRIPOUT_PER_NUM    1 //EPWM8B is peripheral option 1 for GPIO15

void InitCMPSS(void);
void InitEPWM(void);

void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
    InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the F2837xS_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
    InitGpio();
    
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
    DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
    InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
    IER = 0x0000;
    IFR = 0x0000;

    InitPieVectTable();

 // Interrupts that are used in this example are re-mapped to
 // ISR functions found within this file.
    EALLOW;  // This is needed to write to EALLOW protected registers
    PieVectTable.XINT1_INT = &xint1_isr;
    EDIS;   // This is needed to disable write to EALLOW protected registers

 // Enable XINT1 and XINT2 in the PIE: Group 1 interrupt 4 & 5
 // Enable INT1 which is connected to WAKEINT:
    PieCtrlRegs.PIECTRL.bit.ENPIE = 1;          // Enable the PIE block
    PieCtrlRegs.PIEIER1.bit.INTx4 = 1;          // Enable PIE Group 1 INT4
    IER |= M_INT1;                              // Enable CPU INT1
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
    EINT;

// Configure Comparator COMP1H to accept POS input from pin and NEG input from DAC
    InitCMPSS();
// Configure COMP1 to feed TRIP4 EPWM DC trip input
    InitEPWM();

// Configure GPIO15 to output CTRIP1H/EPWM TRIP4
    GPIO_SetupPinMux(   GPIO_CTRIP_PIN_NUM, GPIO_MUX_CPU1,    GPIO_CTRIP_PER_NUM);
// Configure GPIO14 to output CTRIPOUT1H
    GPIO_SetupPinMux(GPIO_CTRIPOUT_PIN_NUM, GPIO_MUX_CPU1, GPIO_CTRIPOUT_PER_NUM);

    GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 2;       // XINT1 Qual using 6 samples
    GpioCtrlRegs.GPACTRL.bit.QUALPRD1 = 0xFF;   // Each sampling window is 510*SYSCLKOUT

    GPIO_SetupXINT1Gpio(14);

 // Configure XINT1
    XintRegs.XINT1CR.bit.POLARITY = 1;      // Rising edge interrupt

 // Enable XINT1
    XintRegs.XINT1CR.bit.ENABLE = 1;        // Enable XINT1

    while(1) 
    {
        // Trip flags set when CTRIP signal is asserted
        if( EPwm8Regs.TZFLG.bit.OST ) 
        {
            EALLOW;
            // Wait for comparator CTRIP to de-assert
            while( Cmpss1Regs.COMPSTS.bit.COMPHSTS );
            // Clear trip flags
            EPwm8Regs.TZCLR.bit.OST     = 1;
            EPwm8Regs.TZCLR.bit.INT     = 1;
            EDIS;
        }
    }
}

interrupt void xint1_isr(void)
{
    Xint1Count++;

    // Acknowledge this interrupt to get more from group 1
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}

void InitCMPSS(void) 
{
    EALLOW;
    //Enable CMPSS
    Cmpss1Regs.COMPCTL.bit.COMPDACE            = 1;
    //NEG signal comes from DAC
    Cmpss1Regs.COMPCTL.bit.COMPHSOURCE         = NEGIN_DAC;
    //Use VDDA as the reference for DAC
    Cmpss1Regs.COMPDACCTL.bit.SELREF           = REFERENCE_VDDA;
    //Set DAC to midpoint for arbitrary reference
    Cmpss1Regs.DACHVALS.bit.DACVAL             = 2048;

// Configure CTRIPOUT path
    //Asynch output feeds CTRIPH and CTRIPOUTH
    Cmpss1Regs.COMPCTL.bit.CTRIPHSEL           = CTRIP_ASYNCH;
    Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL        = CTRIP_ASYNCH;

    Cmpss1Regs.COMPHYSCTL.bit.COMPHYS          = 4; // Enable hysteresis

// Configure CTRIPOUTH output pin
    //Configure OUTPUTXBAR3 to be CTRIPOUT1H
    OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX0 = 0;
    //Enable OUTPUTXBAR3 Mux for Output
    OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX0   = 1;
    EDIS;
}

void InitEPWM(void) 
{
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC       = 0;

    //Configure EPWM to run at SYSCLK
    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 0;
    EPwm8Regs.TBCTL.bit.CLKDIV             = 0;
    EPwm8Regs.TBCTL.bit.HSPCLKDIV          = 0;
    //Initialize dummy values for EPWM CTR/PRD
    EPwm8Regs.TBCTR                        = 0;
    EPwm8Regs.TBPRD                        = 0xFFFF;

    //Configure EPWM8B to output high on TZB TRIP
    EPwm8Regs.TZCTL.bit.TZB                = TZ_FORCE_HI;
    //Configure DCB to be TRIP4
    EPwm8Regs.TZDCSEL.bit.DCBEVT1          = TZ_DCBH_HI;
    EPwm8Regs.DCTRIPSEL.bit.DCBHCOMPSEL    = 0xF; //DCBHTRIPSEL
    EPwm8Regs.DCBHTRIPSEL.bit.TRIPINPUT4   = 1;
    //Configure DCB as OST
    EPwm8Regs.TZSEL.bit.DCBEVT1            = 1;
    //Configure DCB path to be unfiltered & async
    EPwm8Regs.DCBCTL.bit.EVT1SRCSEL        = DC_EVT1;
    EPwm8Regs.DCBCTL.bit.EVT1FRCSYNCSEL    = DC_EVT_ASYNC;

    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC       = 1;

    //Configure TRIP4 to be CTRIP1H
    EPwmXbarRegs.TRIP4MUX0TO15CFG.bit.MUX0 = 0;
    //Enable TRIP4 Mux for Output
    EPwmXbarRegs.TRIP4MUXENABLE.bit.MUX0   = 1;

    // Clear trip flags
    EPwm8Regs.TZCLR.bit.OST                = 1;
    EPwm8Regs.TZCLR.bit.INT                = 1;
    //Enable DCB interrupt
    EPwm8Regs.TZEINT.bit.OST               = 1;

    // Enable PWM
    EPwm8Regs.TBCTL.bit.CTRMODE            = TB_COUNT_UP;

    EDIS;
}

-Tommy

OK so I tried the modified example kindly provided by Tommy - however I am still not out of the woods....

What I am attempting to do is to connect single ended ADC 12 bit compare high outputs to the Output XBAR to any GPIO pins that support muxing to the CMPSS blocks on the 28377S in order to map these outputs for PCB layout. I have pretty much mapped out the complete chip and its resources, however I cannot succesfully map the CMPSS compare high to the Output XBAR - I need help .....HELP!!

I am using the example provided by Tommy. However - I do not need the EPWM stuff. I do not use PWM for this project. I simply need to compare analog inputs and trigger interrupts on ADC channels as fast as possible.

All the example code for CMPSS comparators only explain how to connect one comparator. I need to connect them all - and I am unable to replicate the example to include more comparators to external pins - never mind interrupts. At this stage I just need to observe with my scope probe the switching outputs of each comparator pin.

Could someone please assist with this problem.

Thanks

Nick

I noticed that  the cmpss exampl

Hi Nick,

To get the CMPSS outputs to a pin, use the output x-bar.  For a give output x-bar, you just need to make the following selection:

Once you have made the selection for a given output XBAR, you can get it to the pin by changing the GPIO mux for a pin that has that output XBAR:

Now you should be able to observe it on the pin.  To trigger the ADC, there is a singe input XBAR that you can configure:

This configuration is as easy as picking whatever GPIO you want:

In the ADC SOC configuration logic, you would write '4' to the trigger select to use this as the trigger.

Note that the output XBARs have a big OR gate in them, so you could use multiple CMPSS modules to cause the same ADC trigger, but you can't get multiple CMPSS modules to generate different ADC triggers.

Now if you want to generate an interrupt instead of triggering the ADC, use input Xbars 14, 13, 6, 5, or 4.

Nick,

I noticed a mismatch in the comment statements / #define names in the example code with respect to the GPIO14 and GPIO15 MUX settings.  I hope that isn't throwing you off.

Here's a breakdown of the key configurations.  Hopefully it helps.

-Tommy

OK I have it working now  - the problem seems to be resolved - thank you all very much........for now....

void InitCMPSS1(void);
void InitCMPSS2(void);
void InitCMPSS3(void);
void InitCMPSS4(void);

void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xS_SysCtrl.c file.
InitSysCtrl();

// Step 2. Initialize GPIO:
// This example function is found in the F2837xS_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
InitGpio();

// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;

// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xS_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;

InitPieVectTable();

InitCMPSS1(); // route XBAR 7 to GPIO 16 on ADC_A2: CMPIN1P
InitCMPSS2(); // route XBAR 3 to GPIO 14 on ADC_A4: CMPIN2P
InitCMPSS3(); // route XBAR 1 to GPIO   2 on ADC_B2: CMPIN3P
InitCMPSS4(); // route XBAR 4 to GPIO 15 on ADC_14: CMPIN4P

GPIO_SetupPinMux(16,0,3);// XBAR 7  to ADC_A2

GPIO_SetupPinMux(14,0,6);// XBAR 3 to ADC_A4

GPIO_SetupPinMux(2,0,5);  // XBAR 1 to ADC_B2

GPIO_SetupPinMux(15,0,6);// XBAR 4 to ADC_14

while(1)
{

// do nothing  - idle

}
}

void InitCMPSS1(void)
{
EALLOW;
//Enable CMPSS
Cmpss1Regs.COMPCTL.bit.COMPDACE = 1;
//NEG signal comes from DAC
Cmpss1Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
//Use VDDA as the reference for DAC
Cmpss1Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
//Set DAC to midpoint for arbitrary reference
Cmpss1Regs.DACHVALS.bit.DACVAL = 2048;

// Configure CTRIPOUT path
//Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss1Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;
Cmpss1Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;

Cmpss1Regs.COMPHYSCTL.bit.COMPHYS = 4; // Enable hysteresis

// Configure CTRIPOUTH output pin

OutputXbarRegs.OUTPUT7MUX0TO15CFG.bit.MUX0 = 0;

//Enable OUTPUTXBAR3 Mux for Output
OutputXbarRegs.OUTPUT7MUXENABLE.bit.MUX0 = 1;
EDIS;
}

void InitCMPSS2(void)
{
EALLOW;
//Enable CMPSS
Cmpss2Regs.COMPCTL.bit.COMPDACE = 1;
//NEG signal comes from DAC
Cmpss2Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
//Use VDDA as the reference for DAC
Cmpss2Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
//Set DAC to midpoint for arbitrary reference
Cmpss2Regs.DACHVALS.bit.DACVAL = 2048;//1000;

// Configure CTRIPOUT path
//Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss2Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;
Cmpss2Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;

Cmpss2Regs.COMPHYSCTL.bit.COMPHYS = 4; // Enable hysteresis

// Configure CTRIPOUTH output pin

OutputXbarRegs.OUTPUT3MUX0TO15CFG.bit.MUX2 = 0;

//Enable OUTPUTXBAR3 Mux for Output
OutputXbarRegs.OUTPUT3MUXENABLE.bit.MUX2 = 1;
EDIS;
}

void InitCMPSS3(void)
{
EALLOW;
//Enable CMPSS
Cmpss3Regs.COMPCTL.bit.COMPDACE = 1;
//NEG signal comes from DAC
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
//Use VDDA as the reference for DAC
Cmpss3Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
//Set DAC to midpoint for arbitrary reference
Cmpss3Regs.DACHVALS.bit.DACVAL = 2048;//1000;

// Configure CTRIPOUT path
//Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;
Cmpss3Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;

Cmpss3Regs.COMPHYSCTL.bit.COMPHYS = 4; // Enable hysteresis

// Configure CTRIPOUTH output pin

OutputXbarRegs.OUTPUT1MUX0TO15CFG.bit.MUX4 = 0;

//Enable OUTPUTXBAR3 Mux for Output
OutputXbarRegs.OUTPUT1MUXENABLE.bit.MUX4 = 1;
EDIS;
}

void InitCMPSS4(void)
{
EALLOW;
//Enable CMPSS
Cmpss4Regs.COMPCTL.bit.COMPDACE = 1;
//NEG signal comes from DAC
Cmpss4Regs.COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
//Use VDDA as the reference for DAC
Cmpss4Regs.COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
//Set DAC to midpoint for arbitrary reference
Cmpss4Regs.DACHVALS.bit.DACVAL = 2048;//1000;

// Configure CTRIPOUT path
//Asynch output feeds CTRIPH and CTRIPOUTH
Cmpss4Regs.COMPCTL.bit.CTRIPHSEL = CTRIP_ASYNCH;
Cmpss4Regs.COMPCTL.bit.CTRIPOUTHSEL = CTRIP_ASYNCH;

Cmpss4Regs.COMPHYSCTL.bit.COMPHYS = 4; // Enable hysteresis

// Configure CTRIPOUTH output pin


OutputXbarRegs.OUTPUT4MUX0TO15CFG.bit.MUX6 = 0;

//Enable OUTPUTXBAR3 Mux for Output

OutputXbarRegs.OUTPUT4MUXENABLE.bit.MUX6 = 1;
EDIS;
}