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ADC configuration at 1MHz



CPU TMS320F2837xD

I'm trying to configure an ADC module  to perform the following, 

  • 12-bit operation
  • use 3 channels only  - "configured 3 SOC - last one triggers interrupt to read results"
  • Use timer 2 to trigger ADC conversion at a rate of @1MHz - pretty fast (that is why only 3 channels per module due to 3.5 MSPS - CPU limitation)

I noticed that when I run the ADC at this frequency, the adc result for modules C and D start working and then they stop updating (viewing variable values with debugger) while A and B always update ... my guess is that it has to do with the speed .. because when I reduce it (500KHz), everything works fine 

for reference I choose the following settings, 

AdcaRegs.ADCSOC0CTL.bit.ACQPS   = 23; // Acq Window = 120nsec/5nsec (200MHz) = 24 cycles -1 (counts 0) -> 23

AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;  // waits for conversion to be completed in order to interrupt 

AdcaRegs.ADCCTL2.bit.PRESCALE = 6; // 200Mhz/4 = 50Mhz -> range should be within 5-50Mhz

any Ideas of what could be my issue ?

Thanks 

Dorian~

  • Hi Dorian,

    It should certainly be possible to sample all 4 ADCs at maximum sample rate.  A few thoughts:

    Are you triggering an interrupt from just one ADC, or from all 4?  Since the ADCs are triggered at the same time, it should be possible to use a single interrupt. 

    Depending on what you are trying to do with the data, you may be able to save some additional CPU bandwidth by putting all the ADCs into 'burst mode'.  This will allow you to use maybe 12 of the ADCRESULT registers to buffer 4 sets of conversions, instead of having to read the results right away.  Alternately, you could use normal triggering and slow the trigger down by a factor of 4, and then have each trigger cause 12 conversions where the 3 signals of interest repeat.

    Do the result registers for C and D update sporadically, or not at all?  Do they update at the end if you halt the program?  The JTAG interface is definitely not fast enough to keep up with 4 ADCs updating data at 3 MSPS, so maybe CCS has a bottleneck just trying to update ADCA and ADCB results? You could try sampling the data strictly in the C code into a buffer (maybe 256 conversions per ADC) and then examining them after the program runs to see if the C program ran correctly?

  • *Are you triggering an interrupt from just one ADC, or from all 4? Since the ADCs are triggered at the same time, it should be possible to use a single interrupt.

    // Acq Window = 120nsec/5nsec (200MHz) = 24 cycles -1 (counts 0) -> 23
    Uint8 conv_time = 23;

    // CPU timer 1 - to trigger conversion
    Uint8 trig_source = 2;

    ///////////////
    // ADC A
    ///////////////
    AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; //SOC0 will convert ADCINA0
    AdcaRegs.ADCSOC0CTL.bit.ACQPS = conv_time; //SOC0 will use sample duration
    AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = trig_source; //SOC0 will begin conversion on CPU1 Timer 2

    AdcaRegs.ADCSOC1CTL.bit.CHSEL = 1; //SOC1 will convert ADCINA1
    AdcaRegs.ADCSOC1CTL.bit.ACQPS = conv_time; //SOC1 will use sample duration
    AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = trig_source; //SOC1 will begin conversion on CPU1 Timer 2

    AdcaRegs.ADCSOC2CTL.bit.CHSEL = 2; //SOC2 will convert ADCINA2
    AdcaRegs.ADCSOC2CTL.bit.ACQPS = conv_time; //SOC2 will use sample duration
    AdcaRegs.ADCSOC2CTL.bit.TRIGSEL = trig_source; //SOC2 will begin conversion on CPU1 Timer 2

    /*Sets up Interrupt*/
    AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 2; //end of SOC2 will set INT1 flag
    AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
    AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared


    *Do the result registers for C and D update sporadically, or not at all?

    they start working and then they stop updating ( seems like they keep old value)

    * Do they update at the end if you halt the program?
    No ... I need to restart the controller


    The JTAG interface is definitely not fast enough to keep up with 4 ADCs updating data at 3 MSPS, so maybe CCS has a bottleneck just trying to update ADCA and ADCB results?

    maybe .. i dont expect cycle by cycle accuracy with debugger - it updates at 250msec ... but for ADC's A and B modules ... everything works fine .. as I interact with the pins ... I can see values changing .. no problem

    *You could try sampling the data strictly in the C code into a buffer (maybe 256 conversions per ADC) and then examining them after the program runs to see if the C program ran correctly?

    sure .. to do this i need a new fixture that I currently don't have (change various ADC values .. otherwise I'm going to get zeros ... hard to tell if this is working ) .. again ADC modules A and B work .. only C and D have issues when sampling at 1Mhz .. if I reduce the frequency .. everything is fine !
  • Hi Dorian,

    I am not sure if your code snippet answer's the question. Do you do the same interrupt configuration on every ADC, or just on ADCA? Do you trigger a CPU interrupt through the PIE based on this flag, or do you spin-wait on the flag?
  • Yes, I perform the same interrupt configuration in all 4 ADC modules.

    I use CPU timer 1, configured to trigger an interrupt at 1MHz .. just like in the example .. correct me if I'm wrong but timer 1 does not use PIE, it connects to the CPU directly ... correct ? ... not sure I understand your second question

    Timer->RegsAddr->PRD.all =199 // no prescale
    Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
    Timer->RegsAddr->TCR.bit.SOFT = 0;
    Timer->RegsAddr->TCR.bit.FREE = 0; // Timer Free Run Disabled
    Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt

    lastly during the interrupt .. I don't do anything but increasing a interrupt counter.

    one question .. can I disable timer interrupt ? and when timer 1 times out .. would it still trigger ADC modules .. even if interrupt is disabled ?
  • The team supported in an online meeting ..

    the reason for this issue was 4 interrupts triggering and only 200 CPU cycles available .. so after some time the CPU did not have enogh time to service all the interrupts ..