Cycle-by-Cycle PWM Trip and Sync generation with DCAEVT1

Hi Chengcheng,

Perhaps you could do the following:
Your COMP1 currently generates a DCAH signal (an assumption).  You could then configure DCAH = H and DCAL=Don't Care combination, to generate both a DCAEVT1 event and a DCAEVT2 event.

The DCAEVT1 could then do the synch.  The DCAEVT2 would then be responsible for doing the CBC trip.

Hopefully this helps!


Thank you,
Brett

Hi Brett,

Thanks for your reply. Yes, you are right. My COMP1 currently generates a DCAH signal. My concern is that DCAEVT1 can only do one-shot mode. Can I clear the trigger condition via TZCLR and use DCAEVT1 for CBC trip? If it is possible, I can use DCAEVT1 to do both the SYNC and CBC trip.

Thanks,

Chengcheng

Hi Chengcheng,

No, there is no ability to have DCAEVT1 to do both SYNC and the CBC trip.

However, DCAH can. 

COMP1 -> DCAH -> DCAEVT1 -> SYNC
           |
           |---> DCAEVT2 -> CBC latch

If done as I suggest, DCAEVT1 and DCAEVT2 will both be signals digital signals that directly match the output of the comparator.  Note that any latching is done further downstream, after DCxEVTn.

Hopefully this helps!


Thank you,
Brett

Hi Brett,

Thanks for your additional explanation. I am working your suggested method now. One more question is regarding the DCAEVT2 cycle-by-cyle trip.

In all the TI example codes, I saw the cyle-by-cycle trip was programmed through EPwm2Regs.TZCTL.bit.TZA , Why not EPwm1Regs.TZCTL.bit.DCAEVT1?

Right now once I added the DCAEVT2 trip, the PWM was always low. Meanwhile, only using DCAEVT1 to generate sync gave a 180 ns delay. Could you please take a look at my code?

EALLOW;

//===========================================================================
// Define an event (DCAEVT1) based on Comparator 1 Output
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // DCAH = Comparator 1 output
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW; // DCAEVT2 = DCAH low (will become active as Comparator output goes low)
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = TZ_DCAH_LOW; // DCAEVT2 = DCAH low (will become active as Comparator output goes low)

EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT_FLT; // DCAEVT1 = DC_EVT_FLT (filtered) (Not EVT2SRCSEL????)
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC; // Take async path

EPwm1Regs.DCACTL.bit.EVT2SRCSEL = DC_EVT_FLT; // DCAEVT1 = DC_EVT_FLT (filtered) (Not EVT2SRCSEL????)
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = DC_EVT_ASYNC; // Take async path

// Enable DCAEVT2 as a cycle by cycle trip source
EPwm1Regs.TZSEL.bit.DCAEVT2 = 1; // Enable cycle by cycle trip (only EVT2 can do CBC)
EPwm1Regs.DCACTL.bit.EVT1SYNCE = 1; // Sync enabled

// What do we want the DCAEVT1 event to do?
EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_NO_CHANGE; // No action at the output on DCAEVT1
EPwm1Regs.TZCTL.bit.DCAEVT2 = TZ_FORCE_HI; // EPWMxA - force high


//===========================================================================
// Event Filtering Configuration for DCAEVT1
EPwm1Regs.DCFCTL.bit.SRCSEL = DC_SRC_DCAEVT1;
EPwm1Regs.DCFCTL.bit.BLANKE = DC_BLANK_ENABLE;
EPwm1Regs.DCFCTL.bit.PULSESEL = DC_PULSESEL_ZERO; //Pulse Select For Blanking & Capture Alignment

EPwm1Regs.DCFOFFSET = 0; // Blanking Window Offset = CMPA(n+1)
EPwm1Regs.DCFWINDOW = 0; // Blanking window length - initial value // needs to load the ON time to the window

//===========================================================================
EDIS;

Hi Chengcheng,

Please take a look at the linked figure in the following post:
https://e2e.ti.com/support/microcontrollers/c2000/f/171/p/442905/1591744#1591744
(the figure is true of the F2802x, F2803x, F2805x and F2806x device families and will eventually be put into the datasheet)

The TZCTL[DCxEVTn] settings can be used to do cycle-by-cycle forcing of the PWM output.  (force PWM output high only when COMP1 is high, etc)
The TZCTL[TZA] or TZCTL[TZB] is more often what is desired (and sounds like what you want).


Thank you,
Brett

Hi Chengcheng,

"...I only want to generate a ePWMsynchin on the DCAH falling edge..."
[BL] You get to choose how DCAEVT1 and ECAEVT2 are defined from DCAH. (register TZDCSEL)

"...I measure 80ns delay from the input of COMP1 to ePWM1A.  Is that the best we can do?"
[BL] This seems long to me, especially since the majority of the path taken is asynchronous, I'd expect maybe half what you are seeing.  Some questions:

1. Are you using DCAEVT1 to drive the synchronization pulse? (or the slower DCEVTFILT?)
2. Are you using the comparator's asynch path (SYNCSEL register in the comparator)
3. Is the delay you are measuring consistent, or is there jitter?  I suspect little to no jitter.  If there is no jitter, you can configure the slave PWM's TBPHS register to compensate for the delay you see - and therefore reduce or eliminate the phase offset.

Thank you,
Brett

Hi Chengcheng,

I would expect the trip delay to be smaller than the synch delay.  The circuits that handle the trip functionality in the chip are largely asynchronous.  The synch functionality is at least partially synchronous.

In fact, after looking at this again, the amount of time for a PWM to synch should be approximately 2 to 3 TBCLKs (~50ns).  30ns as the trip time you are measuring + 50ns synch time = 80ns.

===

Another potential option for doing what you are doing is as below:

COMP event occurs ->
PWM CBC trip after ~30ns ->
PWM synch happens ~50ns later, PWM timer is set to TBPRD - 1 via TBPHS ->
1 TBCLK later, the PWM is set to 0.  The CBC event clears here, but the PWM is is also set at the 0 event in the AQ.

Some fine tuning may be necessary - assuming the above is something like what you're wanting.

It is not abundantly clear what you are hoping to accomplish in your project, so you may have to resolve some of this on your own.  However, some of the thought process I've described is hopefully useful.


Thank you,
Brett