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Compute CRC with VCU for TI OTP memory causes MCU to crash?

Shef
Expert 1960 points
Other Parts Discussed in Thread: CONTROLSUITE

Hi Folkd,

I just found a strange issue with my F28377D when using VCU2 to compute CRC for all memory sections. It works fine for all sections except TI OPT section, i.e. from 0x70000 to 0x703FF.  This causes MCU to reset itself somehow when it does it, and the code restart ever and over again. If I comment out this line, everything would work fine. It's strange that the same code (computer CRC with VCU) works fine for all other sections, including user OTP (0x78000-0x783FF) and all flash sectors, A-F.

However, if I run the code from CCS debugger, it will work fine without reset. But if I disconnect CCS and run it from power-on reset, it will reset itself over and over again, until I comment out the line and reprogram the memory.

I'll appreciate it very much if anyone can offer any clue. Thanks!

  • 0
    TI__Guru** 115271 points

    Hi Shef,

    From the description, it look like there is ECC error while accessing the OTP. Since ECC is disabled when connected to debugger this may not be causing issue with debugger connected.

    NMISHDFLG register has status bit for ECC error. Please check the same to see if this is indeed the issue.

    Regards,

    Vivek Singh 

  • 0
    TI__Guru* 87145 points

    Shef,

    TI intentionally inserts ECC errors in below TI-OTP locations.  Applications that require to check the health of the SECDED (ECC) logic at run time can read below locations and check whether ECC logic is able to capture these errors or not.  Your application is reading these locations in your VCU CRC check - this causes an uncorrectable ECC error leading to NMI.

    Address

    64-bit data programmed by TI at this address

    Corresponding ECC address

    ECC data programmed by TI at this address

    Type of error

    0x701F8

    0x9ABCDEF112345678

    0x107003F (LSB 8-bits)

     

    0x9907

    Single-bit error

     

    0x701FC

    0x9ABCDEF312345678

    0x107003F (MSB 8-bits)

     

    0x9907

    Double-bit (uncorrectable) error

    As mentioned in the TRM, there are two SECDED modules in the Flash wrapper. Out of the 128-bits returned from Flash/OTP for an access, both the lower 64-bits and the upper 64-bits are evaluated for ECC in parallel. Hence, although ECC is calculated on 64-bit basis, a read of any address location within a 128-bit aligned Flash memory will cause the un-correctable error flag to get set when there is a un-correctable error in both or in either one of the lower 64 and upper 64 bits of that 128-bit data. NMI will occur for a read of any address location within a 128-bit aligned Flash memory, when there is an un-correctable error in both or in either one of the lower 64 and upper 64 bits of that 128-bit data.  Since single-bit error and un-correctable error exist in the same 128-bits in above addresses, NMI will occur even when the lower 64-bits (0x701F8) are accessed.  

    Avoid reads to the 128-bit data at address 0x701F8 - 0x0x701FF and that should fix your issue.

    Our documentation team is working on providing the above details in the TRM.

    Thanks and regards,

    Vamsi

  • 0 in reply to Vamsi Gudivada
    Expert 1960 points
    Thank you both Vivek and Vamsi! You guys are exactly right. It's indeed the ECC. If I limit TI OTP reading before 0x701F8, there will be no problem. This is actually a good way to test my NMI ISR too.

    However, Vivek, while testing the code in CCS, I did NOT see NMISHDFLG register change at all even when my code does read the ECC region. Is it because that ECC is disabled during debug mode? If so, how do I see the NMISHDFLG register value otherwise? During run-time (after initial power-on self test), I configured ISR for NMI (instead of reset MCU). But I still don't see NMISHDFLG changing at all after the code reading ECC region. Just curious why.
  • 0 in reply to Shef
    TI__Guru* 87145 points

    Shef,

    Do you have ECC enabled in your code before reading the OTP space (below code enables ECC)?  ECC is enabled at power-up but it gets disabled by the gel file (in the debugger connected case).  Hence, you should enable ECC in your code to get the un-correctable ECC error registered in NMISHDFLG.     

    EALLOW;
    Flash0EccRegs.ECC_ENABLE.bit.ENABLE = 0xA;
    EDIS;

    You can use InitFlash() function from Controlsuite.  This function configures the Flash wait-states and enables ECC.

    Note:  In your NMI ISR, you need to clear the UNC_ERR_INTFLG (refer to FLASH_ECC_REGS Registers in TRM section 2.14.23 @ http://www.ti.com/lit/ug/spruhm8e/spruhm8e.pdf) along with NMIFLG.FLUNCERR and NMIFLG.NMIINT if the NMI ISR is invoked because of the Flash uncorrectable error.       

    Thanks and regards,

    Vamsi