I am facing issue with respect to the Timer controller (TMS320F28335PGFA).
Following are the details,
I have configured the timer (CPUTimer 0) for 312.5us. But while verifying it using Oscilloscope it is observed that it is fluctuating upto 320us - 340us. While analysing the same I observed that whenever I comment the task of updating the data from external memory (SRAM), the fluctuation stops.
The updation task is performed by using memcpy() and comparison using memset() function. I modified it using for loop instead and found it works and timer ticks properly. Kindly let me know if there is any dependency of external memory operation and timer tick interrupt operation.
I am using SRAM interface at Zone7 memory location (0x20 0000). Also I am using DMA Channel 1 for Reading the data from SRAM and Channel 2 for Writing the data to SRAM.The Location for the other SRAM is (0x0004000).
Is there any dependency of DMA operation as well for affecting the Timer tick? since while checking only for Timer tick it works fine and tick is observed upto 313us.
Please find attached files for reference
- CPU Timer initialization routine
- Xintf file
- CMD file for memory allocation
/**********************************************************
CPU Timer functions (TMS320F28335PGFA)
**********************************************************/
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float32_t Freq, float32_t Period)
{
uint32_t temp;
Timer->RegsAddr->TCR.bit.TSS = 1;// Stop CPU Timer0 add for variable sampling rate
// Initialize timer period:
Timer->CPUFreqInMHz = Freq;
Timer->PeriodInUSec = Period;
temp = (uint32_t) (Freq * Period);
Timer->RegsAddr->PRD.all = temp;
// Set pre-scale counter to divide by 1 (SYSCLKOUT):
Timer->RegsAddr->TPR.all = 0;
Timer->RegsAddr->TPRH.all = 0;
// Initialize timer control register:
Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
Timer->RegsAddr->TCR.bit.SOFT = 1;
Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run
Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
// Reset interrupt counter:
Timer->InterruptCount = 0;
Timer->RegsAddr->TCR.bit.TSS = 0;// Start CPU Timer0 add for variable sampling rate
}
/******************************************************************/
void InitCpuTimer0InterruptSetting(void)
{
EALLOW;
PieVectTable.TINT0 = &cpu_timer0_isr;
EDIS;
PieCtrlRegs.PIEIER1.bit.INTx7=1; // Enable PIE Group 12, INT 1
IER |= M_INT1;
}
/******************************************************************/
Function Call:
ConfigCpuTimer(&CpuTimer0, 100, 312.5);
/*
// TI File $Revision: 1.4 $
// Checkin $Date: 2011/09/02 06:48:34 $
//###########################################################################
//
// FILE: F28335.cmd
//
// TITLE: Linker Command File For F28335 Device
//
//###########################################################################
// $TI Release: DSP2833x/DSP2823x C/C++ Header Files V1.31 $
// $Release Date: August 4, 2009 $
//###########################################################################
*/
/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\DSP2833x_Headers\cmd
//
// For BIOS applications add: DSP2833x_Headers_BIOS.cmd
// For nonBIOS applications add: DSP2833x_Headers_nonBIOS.cmd
========================================================= */
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map */
/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP2833x_Headers_nonBIOS.cmd */
/* Uncomment this line to include file only for BIOS applications */
/* -l DSP2833x_Headers_BIOS.cmd */
/* 2) In your project add the path to <base>\DSP2833x_headers\cmd to the
library search path under project->build options, linker tab,
library search path (-i).
/*========================================================= */
/* Define the memory block start/length for the F28335
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F28335 are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
L0/L1/L2 and L3 memory blocks are mirrored - that is
they can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks can be combined
if required to create a larger memory block.
*/
MEMORY
{
PAGE 0: /* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
ZONE0 : origin = 0x004000, length = 0x001000 /* XINTF zone 0 */
RAML0 : origin = 0x008000, length = 0x002DD0 /* on-chip RAM block L0 */ //Sandeep //3fd0
RAML1 : origin = 0x00ADD0, length = 0x1210 /* on-chip RAM block L1 */// 0x00BFD0
RAML2 : origin = 0x00BFE0, length = 0x0010 /* on-chip RAM block L2 */
RAML3 : origin = 0x00BFF0, length = 0x0010 /* on-chip RAM block L3 */
ZONE6 : origin = 0x0100000, length = 0x100000 /* XINTF zone 6 */
// ZONE7A : origin = 0x0200000, length = 0x100000 /* XINTF zone 7 - program space */
FLASHH : origin = 0x300000, length = 0x008000 /* on-chip FLASH */
FLASHG : origin = 0x308000, length = 0x008000 /* on-chip FLASH */
FLASHF : origin = 0x310000, length = 0x008000 /* on-chip FLASH */
FLASHE : origin = 0x318000, length = 0x002000 /* on-chip FLASH */
FLASHD : origin = 0x31A000, length = 0x014000 /* on-chip FLASH */
FLASHC : origin = 0x32E000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x338000, length = 0x007F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x33FF80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x33FFF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x33FFF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
OTP : origin = 0x380400, length = 0x000400 /* on-chip OTP */
ADC_CAL : origin = 0x380080, length = 0x000009 /* ADC_cal function in Reserved memory */
IQTABLES : origin = 0x3FE000, length = 0x000b50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008c /* IQ Math Tables in Boot ROM */
FPUTABLES : origin = 0x3FEBDC, length = 0x0006A0 /* FPU Tables in Boot ROM */
ROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 : /* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
RAML4 : origin = 0x00C000, length = 0x001000 /* on-chip RAM block L1 */
RAML5 : origin = 0x00D000, length = 0x003000 /* on-chip RAM block L1 */
ZONE7A : origin = 0x200000, length = 0x100000 /* XINTF zone 7 - data space */
// ZONE7B : origin = 0x20FC00, length = 0x000400 /* XINTF zone 7 - data space */
FLASHB : origin = 0x330000, length = 0x008000 /* on-chip FLASH */
}
/* Allocate sections to memory blocks.
Note:
codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
execution when booting to flash
ramfuncs user defined section to store functions that will be copied from Flash into RAM
*/
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHC PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHD PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = RAML0,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/*
RYOsc_SECT :> ZONE7A PAGE = 0
PAL_VAR_SECT :> ZONE7A PAGE = 0
COMP_LOGIC_VAR_SECT :> ZONE7A PAGE = 0
PROSet_SECT :> ZONE7A PAGE = 0
*/
RYOsc_SECT :> ZONE7A PAGE = 1
PAL_VAR_SECT :> ZONE7A PAGE = 1
COMP_LOGIC_VAR_SECT :> ZONE7A PAGE = 1
PROSet_SECT :> ZONE7A PAGE = 1
/* Allocate uninitalized data sections: */
/* .stack : > RAMM1 PAGE = 1*/
.stack : > RAMM1 | RAMM0, PAGE = 1
.ebss : > RAML0 PAGE = 0
.esysmem : > RAMM1 PAGE = 1
//FFTipcb ALIGN(128) : { } > RAML0 PAGE 0
//FFTmag > RAML0 PAGE 0
FFTipcb ALIGN(128) : { } > RAML4 PAGE 1
FFTmag > RAML4 PAGE 1
FFTtf > FLASHA PAGE 0 /* Non volatile mem */
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHD PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
/*IQmath : > FLASHC PAGE = 0 */ /* Math Code */
/*IQmathTables : > IQTABLES, PAGE = 0, TYPE = NOLOAD*/
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
buff1 : > RAML0, PAGE = 0
DaqFFTVar : > RAML1, PAGE = 0
FPUmathTables : > FPUTABLES, PAGE = 0, TYPE = NOLOAD
/* Allocate DMA-accessible RAM sections: */
DMARAML4 : > RAML4, PAGE = 1
COMMONRAM5_SECT : > RAML5 PAGE = 1
/* Allocate 0x400 of XINTF Zone 7 to storing data */
// ZONE7DATA : > ZONE7B, PAGE = 1
/* .reset is a standard section used by the compiler. It contains the */
/* the address of the start of _c_int00 for C Code. /*
/* When using the boot ROM this section and the CPU vector */
/* table is not needed. Thus the default type is set here to */
/* DSECT */
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
/* Allocate ADC_cal function (pre-programmed by factory into TI reserved memory) */
.adc_cal : load = ADC_CAL, PAGE = 0, TYPE = NOLOAD
}
/*
//===========================================================================
// End of file.
//===========================================================================
*/
// TI File $Revision: 1.2 $
// Checkin $Date: 2012/01/03 04:23:34 $
//###########################################################################
//
// FILE: DSP2833x_Xintf.c
//
// TITLE: DSP2833x Device External Interface Init & Support Functions.
//
// DESCRIPTION:
//
// Example initialization function for the external interface (XINTF).
// This example configures the XINTF to its default state. For an
// example of how this function being used refer to the
// examples/run_from_xintf project.
//
//###########################################################################
// $TI Release: 2833x/2823x Header Files V1.32 $
// $Release Date: June 28, 2010 $
//###########################################################################
#include "DSP2833x_Device.h" // DSP2833x Headerfile Include File
#include "DSP2833x_Examples.h" // DSP2833x Examples Include File
//---------------------------------------------------------------------------
// InitXINTF:
//---------------------------------------------------------------------------
// This function initializes the External Interface the default reset state.
//
// Do not modify the timings of the XINTF while running from the XINTF. Doing
// so can yield unpredictable results
void InitXintf(void);
void InitXintf(void)
{
// This shows how to write to the XINTF registers. The
// values used here are the default state after reset.
// Different hardware will require a different configuration.
// For an example of an XINTF configuration used with the
// F28335 eZdsp, refer to the examples/run_from_xintf project.
// Any changes to XINTF timing should only be made by code
// running outside of the XINTF.
// All Zones---------------------------------
// Timing for all zones based on XTIMCLK = 1/2 SYSCLKOUT
EALLOW;
XintfRegs.XINTCNF2.bit.XTIMCLK = 0;
// No write buffering
XintfRegs.XINTCNF2.bit.WRBUFF = 0;
// XCLKOUT is enabled
XintfRegs.XINTCNF2.bit.CLKOFF = 0;
// XCLKOUT = XTIMCLK/2
XintfRegs.XINTCNF2.bit.CLKMODE =0 ;
// Zone 0------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
#if 1 // NH - New settings as per HW change
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 1;
XintfRegs.XTIMING0.bit.XWRACTIVE = 3;
XintfRegs.XTIMING0.bit.XWRTRAIL = 0;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 1;
XintfRegs.XTIMING0.bit.XRDACTIVE = 3;
XintfRegs.XTIMING0.bit.XRDTRAIL = 0;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 0;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 0;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
#else
// Zone write timing
XintfRegs.XTIMING0.bit.XWRLEAD = 3;
XintfRegs.XTIMING0.bit.XWRACTIVE = 7;
XintfRegs.XTIMING0.bit.XWRTRAIL = 3;
// Zone read timing
XintfRegs.XTIMING0.bit.XRDLEAD = 3;
XintfRegs.XTIMING0.bit.XRDACTIVE = 7;
XintfRegs.XTIMING0.bit.XRDTRAIL = 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING0.bit.X2TIMING = 1;
// Zone will sample XREADY signal
XintfRegs.XTIMING0.bit.USEREADY = 1;
XintfRegs.XTIMING0.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING0.bit.XSIZE = 3;
#endif
// Zone 6------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
// Zone write timing
XintfRegs.XTIMING6.bit.XWRLEAD = 1;//3;
XintfRegs.XTIMING6.bit.XWRACTIVE = 3;//7;
XintfRegs.XTIMING6.bit.XWRTRAIL = 0;//3;
// Zone read timing
XintfRegs.XTIMING6.bit.XRDLEAD = 1;//3;
XintfRegs.XTIMING6.bit.XRDACTIVE = 3;//7
XintfRegs.XTIMING6.bit.XRDTRAIL =0;// 3;
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING6.bit.X2TIMING = 0;//1;
// Zone will sample XREADY signal
XintfRegs.XTIMING6.bit.USEREADY = 0;//1;
XintfRegs.XTIMING6.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING6.bit.XSIZE = 3;
// Zone 7------------------------------------
// When using ready, ACTIVE must be 1 or greater
// Lead must always be 1 or greater
#if 1 // NH - as per new HW changes
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
XintfRegs.XTIMING7.bit.XWRACTIVE = 2;
XintfRegs.XTIMING7.bit.XWRTRAIL = 0;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
XintfRegs.XTIMING7.bit.XRDACTIVE = 2;
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
#else
// Zone write timing
XintfRegs.XTIMING7.bit.XWRLEAD = 1;
XintfRegs.XTIMING7.bit.XWRACTIVE = 0;
XintfRegs.XTIMING7.bit.XWRTRAIL = 0;
// Zone read timing
XintfRegs.XTIMING7.bit.XRDLEAD = 1;
XintfRegs.XTIMING7.bit.XRDACTIVE = 1;
XintfRegs.XTIMING7.bit.XRDTRAIL = 0;
#endif
// double all Zone read/write lead/active/trail timing
XintfRegs.XTIMING7.bit.X2TIMING = 0;
// Zone will sample XREADY signal
XintfRegs.XTIMING7.bit.USEREADY = 0;
XintfRegs.XTIMING7.bit.READYMODE = 1; // sample asynchronous
// Size must be either:
// 0,1 = x32 or
// 1,1 = x16 other values are reserved
XintfRegs.XTIMING7.bit.XSIZE = 3;
// Bank switching
// Assume Zone 7 is slow, so add additional BCYC cycles
// when ever switching from Zone 7 to another Zone.
// This will help avoid bus contention.
#if 1 // NH
XintfRegs.XBANK.bit.BANK = 0; //6
XintfRegs.XBANK.bit.BCYC = 2; //6
#else
XintfRegs.XBANK.bit.BANK = 6;
XintfRegs.XBANK.bit.BCYC = 6;
#endif
EDIS;
//Force a pipeline flush to ensure that the write to
//the last register configured occurs before returning.
// InitXintf16Gpio();
// InitXintf32Gpio();
asm(" RPT #7 || NOP");
}
void InitXintf32Gpio()
{
EALLOW;
GpioCtrlRegs.GPBMUX2.bit.GPIO48 = 3; // XD31
GpioCtrlRegs.GPBMUX2.bit.GPIO49 = 3; // XD30
GpioCtrlRegs.GPBMUX2.bit.GPIO50 = 3; // XD29
GpioCtrlRegs.GPBMUX2.bit.GPIO51 = 3; // XD28
GpioCtrlRegs.GPBMUX2.bit.GPIO52 = 3; // XD27
GpioCtrlRegs.GPBMUX2.bit.GPIO53 = 3; // XD26
GpioCtrlRegs.GPBMUX2.bit.GPIO54 = 3; // XD25
GpioCtrlRegs.GPBMUX2.bit.GPIO55 = 3; // XD24
GpioCtrlRegs.GPBMUX2.bit.GPIO56 = 3; // XD23
GpioCtrlRegs.GPBMUX2.bit.GPIO57 = 3; // XD22
GpioCtrlRegs.GPBMUX2.bit.GPIO58 = 3; // XD21
GpioCtrlRegs.GPBMUX2.bit.GPIO59 = 3; // XD20
GpioCtrlRegs.GPBMUX2.bit.GPIO60 = 3; // XD19
GpioCtrlRegs.GPBMUX2.bit.GPIO61 = 3; // XD18
GpioCtrlRegs.GPBMUX2.bit.GPIO62 = 3; // XD17
GpioCtrlRegs.GPBMUX2.bit.GPIO63 = 3; // XD16
GpioCtrlRegs.GPBQSEL2.bit.GPIO48 = 3; // XD31 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO49 = 3; // XD30 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO50 = 3; // XD29 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO51 = 3; // XD28 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO52 = 3; // XD27 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO53 = 3; // XD26 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO54 = 3; // XD25 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO55 = 3; // XD24 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO56 = 3; // XD23 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO57 = 3; // XD22 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO58 = 3; // XD21 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO59 = 3; // XD20 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO60 = 3; // XD19 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO61 = 3; // XD18 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO62 = 3; // XD17 asynchronous input
GpioCtrlRegs.GPBQSEL2.bit.GPIO63 = 3; // XD16 asynchronous input
InitXintf16Gpio();
}
void InitXintf16Gpio()
{
EALLOW;
GpioCtrlRegs.GPCMUX1.bit.GPIO64 = 3; // XD15
GpioCtrlRegs.GPCMUX1.bit.GPIO65 = 3; // XD14
GpioCtrlRegs.GPCMUX1.bit.GPIO66 = 3; // XD13
GpioCtrlRegs.GPCMUX1.bit.GPIO67 = 3; // XD12
GpioCtrlRegs.GPCMUX1.bit.GPIO68 = 3; // XD11
GpioCtrlRegs.GPCMUX1.bit.GPIO69 = 3; // XD10
GpioCtrlRegs.GPCMUX1.bit.GPIO70 = 3; // XD19
GpioCtrlRegs.GPCMUX1.bit.GPIO71 = 3; // XD8
GpioCtrlRegs.GPCMUX1.bit.GPIO72 = 3; // XD7
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 3; // XD6
GpioCtrlRegs.GPCMUX1.bit.GPIO74 = 3; // XD5
GpioCtrlRegs.GPCMUX1.bit.GPIO75 = 3; // XD4
GpioCtrlRegs.GPCMUX1.bit.GPIO76 = 3; // XD3
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 3; // XD2
GpioCtrlRegs.GPCMUX1.bit.GPIO78 = 3; // XD1
GpioCtrlRegs.GPCMUX1.bit.GPIO79 = 3; // XD0
GpioCtrlRegs.GPBMUX1.bit.GPIO40 = 3; // XA0/XWE1n
GpioCtrlRegs.GPBMUX1.bit.GPIO41 = 3; // XA1
GpioCtrlRegs.GPBMUX1.bit.GPIO42 = 3; // XA2
GpioCtrlRegs.GPBMUX1.bit.GPIO43 = 3; // XA3
GpioCtrlRegs.GPBMUX1.bit.GPIO44 = 3; // XA4
GpioCtrlRegs.GPBMUX1.bit.GPIO45 = 3; // XA5
GpioCtrlRegs.GPBMUX1.bit.GPIO46 = 3; // XA6
GpioCtrlRegs.GPBMUX1.bit.GPIO47 = 3; // XA7
GpioCtrlRegs.GPCMUX2.bit.GPIO80 = 3; // XA8
GpioCtrlRegs.GPCMUX2.bit.GPIO81 = 3; // XA9
GpioCtrlRegs.GPCMUX2.bit.GPIO82 = 3; // XA10
GpioCtrlRegs.GPCMUX2.bit.GPIO83 = 3; // XA11
GpioCtrlRegs.GPCMUX2.bit.GPIO84 = 3; // XA12
GpioCtrlRegs.GPCMUX2.bit.GPIO85 = 3; // XA13
GpioCtrlRegs.GPCMUX2.bit.GPIO86 = 3; // XA14
GpioCtrlRegs.GPCMUX2.bit.GPIO87 = 3; // XA15
GpioCtrlRegs.GPBMUX1.bit.GPIO39 = 3; // XA16
GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 3; // XA17
GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 3; // XA18
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19
// GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 3; // XA19 //Sandeep
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 3; // XREADY
// GpioCtrlRegs.GPBMUX1.bit.GPIO35 = 3; // XRNW //Sandeep - used for card detection
GpioCtrlRegs.GPBMUX1.bit.GPIO38 = 3; // XWE0
GpioCtrlRegs.GPBMUX1.bit.GPIO36 = 3; // XZCS0
GpioCtrlRegs.GPBMUX1.bit.GPIO37 = 3; // XZCS7
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6
// GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 3; // XZCS6 //Sandeep
EDIS;
}
//===========================================================================
// No more.
//===========================================================================
