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Synchronization of two interrupts on two Delfinos: C2000 forum

Tihomir Zilic
Intellectual 350 points

Other Parts Discussed in Thread: CONTROLSUITE

Dear,

I asked for a help on MSP Low-Power forum (see post on: e2e.ti.com/.../1890528 and I didn't get the final answer because I wanted specific answer about Delfino microcontroller.

Could you see my problem at the post and try to help?

In short my first post was: "I have two Delfino F28377D microcontrollers. In both of them I implemented the same interrupt routine which triggers every one millisecond. In these interrupts I want to send/receive data using SPI communication. My question is how can I synchronize triggering of these two interrupts on these two Delfinos, because I want to be sure that sending data over SPI will be exactly in the same interrupt on both Delfinos."

The proposed solution: "One processor could trigger the other processor... and itself. Meaning you route GPIO output of master processor to GPIO_with_IRQ_trigger input of each - slave and master processor. Then if CPU clocks are similar and busses of CPU's are not busy, you have pretty synchronous GPIO IRQ trigger ISR calls on both."

But, I got no answer to: "It seems to me like a good solution, but could you give me more details for specific Delfino F28377D microcontroller. Or some example how to set (and which) registers...  I am reading Delfino tutorial to figure out your solution, but could you look at www.ti.com/.../sprs880g.pdf find 'Figure 5-7. Clocking System' and 'Page 74. Interrupts', and please try to propose the way how to do it."

Thank you!

  • 0
    TI__Guru* 93800 points
    Tihomir,

    There are a number of examples in controlSUITE that could help you. The external interrupt example shows how to set this up and the toggle GPIO example shows how to pull a pin high/low.

    <install_dir>\device_support\F2837xD\<version>\F2837xD_examples_Cpu1\external_interrupt and gpio_toggle

    The link you posted is for the data manual. The Technical Reference Manual will have more information on interrupts and GPIO

    www.ti.com/lit/SPRUHM8


    Regards
    Lori
  • 0 in reply to Lori Heustess
    Intellectual 350 points

    Dear Lori,

    thank you for your help!

    It seems to me that external interrupt example could solve this problem. I will try to implement it in my program.

    Have a good day!

    Tihomir

  • 0 in reply to Tihomir Zilic
    Guru 46710 points
    Two more cents:
    If you know worst case interrupt latency of the slave, then you can let master to wait predefined time after CS assertion. Actually this is how most of the SPI slave devices are implemented - they want some time after CS assertion before first clock pulse. You can go this way too.