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Parallel interface with TMS320f28377D

user4565873
Expert 1250 points

Other Parts Discussed in Thread: TMS320F28377D

Hello,

We are designing a 16 bits data bits parellel interface between a TMS320F28377D, a FPGA and a resolver connected to the EMI1 interface via EM1CS0 and EM1CS2.

All questions are based on the analysis of the spruhm8e.pdf

- Connection: Can you confirm: As the data bus is 16 bits, The EM1BA[1] (and not the EM1BA[0] ) must be connected to the A0 of the 2 components, then EM1A0 to A1 (of the 2 components) and so on? (Figure25-9 of the spruhm8e.pdf p2430)

- Timing: Is there any specification of the timing between the adress valid on the EM1A and EM1BA and the EM1CS falling. Our resolver need a minimum of 2ns for read or write operations. (see table 25-21 of the DSP technical datasheet) . I did not find any information on this timing or register to set it.

Thank you,

Regards.

 

  • 0
    TI__Guru** 116581 points

    Hi,

    - Connection: Can you confirm: As the data bus is 16 bits, The EM1BA[1] (and not the EM1BA[0] ) must be connected to the A0 of the 2 components, then EM1A0 to A1 (of the 2 components) and so on? (Figure25-9 of the spruhm8e.pdf p2430)

    Yes, this is correct. Please note that CS0 is for SDRAM interface and not for ASYNC. You need to use CS2 and CS3 for the same.

    - Timing: Is there any specification of the timing between the adress valid on the EM1A and EM1BA and the EM1CS falling. Our resolver need a minimum of 2ns for read or write operations. (see table 25-21 of the DSP technical datasheet) . I did not find any information on this timing or register to set it.

    Please refer the datasheet for timing information. Also 2ns (500MHz) for READ looks very aggressive. This look like a typo. Please double check this number.

    Regards,

    Vivek Singh