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Concerto F28M35H52C1 UART FIFO Rx Timeout Operation

Stephen Ciricillo
Intellectual 430 points

Referring to SPRUH22G Concerto Technical Reference Manual, section 23.3.8:

"The receive timeout interrupt is asserted when the receive FIFO is not empty, and no further data is received over a 32-bit period."

1) This implies that FIFO operation must be enabled in order to fire a Rx Timeout Interrupt.  So my wish to detect excessive gaps between consecutive received characters can only be satisfied in  a mode of operation that includes the FIFO, correct?

2) Also, do Rx Timeout Interrupts have to be enabled for the RTRIS flag to be set in the RTRIS register?  I am inspired to ask this by virtue of an old post on this site.  The poster was unable to see the Rx Timeout Flag unless Rx Timeout Interrupts were also enabled, which prevented polling for the timeout event..

Edit: Never mind on question 2. I see in the Errata sprz357k that there is an issue with RTRIS setting for polled operation.

Thank you,

Steve C.

  • 0
    Guru 30330 points
    Steve,

    I am confirming with the design. From my bench testing it looks like the FIFO does not need to be enabled for the Rx Timeout to be triggered.

    I will let you know what I find out.

    Thanks,
    Mark
  • 0 in reply to Mark Labbato
    Intellectual 430 points
    Hi Mark,
    Bumping this because I am waiting on the 1st question and have an additional one too.
    Question 1: (repeating) Does the FIFO need to be enabled in order for the Receive Timeout to occur?
    Question 2: answered.
    Question 3: (new) Once receive timeout occurs and it is reset, will it continue to occur and need to be reset every 32 bit times until characters begin coming into the UART?
    Thank you,
    Steve C.