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Pie Interrupt General question.

Conner Shoop
Prodigy 70 points

Other Parts Discussed in Thread: CONTROLSUITE

Hello,

I am new to coding on TI devices.  I am currently looking at the adc_soc-epwm_cpu01 example for the delfino c2000 F28377S Launchpad. I think I understand the interrupt pattern; how the ePWM periodically triggers SOC0, and an interrupt stores the value in a buffer.  However, I am confused by two lines and what they actually mean:

//enable PIE interrupt
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

//sync ePWM
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

These lines also give me consistency errors when I try and use a DAC.  I am modeling the DAC usage off of controlSUITE examples as well.  

Can someone please explain what these commands are doing.  Bonus for any tips forconfiguring an ADC with the DAC.  I am using CCSv6 as well.

Best,

Conner Shoop

  • Guru 192875 points

    Hi Conner,

    Conner Shoop said:
    //enable PIE interrupt
    PieCtrlRegs.PIEIER1.bit.INTx1 = 1;

    You need to refer the Interrupt Vector Table: TABLE-2.5 in TRM. The above line means that you've enabled the ADCA1 interrupt that belongs to P1.1

    Conner Shoop said:
    //sync ePWM
    EALLOW;
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    The TBCLKSYNC bit in the peripheral clock enable registers allows all users to globally synchronize all enabled ePWM modules to the time-base clock (TBCLK). When set, all enabled ePWM module clocks are started with the first rising edge of TBCLK aligned. For perfectly synchronized TBCLKs, the prescalers for each ePWM module must be set identically.

    Please refer Section 12.2.2.3.2 in TRM.

    Regards,

    Gautam