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DSCM on 28377D

Other Parts Discussed in Thread: UNIFLASH

Hi,

I get an error, when I program Z1-GRABSEC with 0x15555555 to secure all flash sectors to Z1 and try to "Unlock" with the Z1-CSMPSWD.

UniFlash Console:

[14:55:56] Begin Unlock operation.
[14:55:57] C28xx_CPU1: GEL Output:
Memory Map Initialization Complete

[14:55:57] ERROR >> C28xx_CPU1: Failed Software Reset: A reset is already in progress: (Error -1041 @ 0x0) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 6.0.83.1)

[14:56:02] ERROR >> C28xx_CPU1: Trouble Halting Target CPU: (Error -1135 @ 0x3FEAC2) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 6.0.83.1)

[14:56:02] ERROR >> C28xx_CPU1: Error: (Error -1135 @ 0x3FEAC2) The debug probe reported an error. Confirm debug probe configuration and connections, reset the debug probe, and retry the operation. (Emulation package 6.0.83.1)

[14:56:02] ERROR >> C28xx_CPU1: Unable to determine target status after 20 attempts

[14:56:02] ERROR >> C28xx_CPU1: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging

[14:56:02] Operation Unlock returned.

The DSP runs with normal operation and an alive-LED is blinking. When I try to unlock the LED stops blinking.

When I program only a Z1-CSMPSWD without Z1-GRABSEC I can lock and unlock my DSP without any trouble.

When I lock the CPU2, there are no problems even with Z1-GRABSEC = 0x15555555

  • Hi,

    Are you getting error while connecting to CCS or only when trying to UNLOCK? If getting error while connecting to CCS then please try changing the BOOT PIN setting to Wait BOOT. That should fix the issue (please refer section 2.13.1.1 Emulation Code Security Logic (ECSL)) in TRM for more detail on this.

    Regards,

    Vivek Singh