[F28377S] EPWM Module interleaving synchronization doesnt work

Hi k3y4r,

Works like a charm...

But, I just dont have any idea how it works,

can you please explain me on following explaination I had from datasheet:

This event is ORed with the EPWMxSYNCI input of the ePWM module.
SWFSYNC is valid (operates) only when EPWMxSYNCI is selected by SYNCOSEL = 00

and do you have any idea why the code I provide works on F28027 and F28035, but doesn't work on F28277S?

hi,
for your epwm module 7 and 8 YOU have configured SYNCOSEL = 00 :)

thats why it works.

I just realize,,,the main reason my original code doesn't work, because the EPWMxSYNCIN for F28377S has completely different structure compared to F28027 and F28035, because F28377S use Type-4 EPWM Scheme, instead of Type-1 EPWM Scheme on F28027 or F28035.

Thus, I can't synchronize EPWM7 and EPWM8 from EPWM6, since according to the Type-4 Scheme, the EPWM6SYNCOUT is not connected to EPWM7SYNCIN. Instead, EPWM7SYNCIN connected to EPWM1SYNCOUT. So, to make it work I simply initialize EPWM1 and use EPWM1SYNCOUT as SYNCIN for EPWM6, EPWM7, and EPWM8.

FYI, I used F28027 and F28035 for my previous projects.

Hi,
Can you share your synchronize code, I try to synchronizze the EWPM2A-2B and EPWM3 but I haave a problem.

Hi Enes,

please pay attention on the Synchronization chain architecture above,

as you can see, that the synchronization is now grouped into several sync chain, and only the EPWM channel located on top of the chain can generate sync signal.

So in this case, you should use EPWM1 to synchronize your EPWM2 and EPWM3

void ConfigureEPWM(void) {
	// Assumes ePWM1 clock is already enabled in InitSysCtrl();
	EALLOW;
	ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV	= 0x0001;
	EDIS;
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0x0;
	EDIS;

	EPwm1Regs.ETSEL.bit.SOCAEN	= 1;		// Enable SOC on A group
	EPwm1Regs.ETSEL.bit.SOCASEL	= 1;		// Select SOC from from CPMA on upcount
	EPwm1Regs.ETPS.bit.SOCAPRD 	= 1;		// Generate pulse on 1st event

	//=====================================================================
	// Configuration
	//=====================================================================
	// Initialization Time
	//========================// EPWM Module 1 config
	EPwm1Regs.TBPRD = PWM_PRD; // Period = 1600 TBCLK counts
	EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
	EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
	EPwm1Regs.TBPHS.bit.TBPHS = 0; // Set Phase register to zero
	EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
	EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
	EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM1A
	EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
	EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Low complementary
	EPwm1Regs.DBFED = PWM_DB; // FED = 50 TBCLKs
	EPwm1Regs.DBRED = PWM_DB; // RED = 50 TBCLKs
	// EPWM Module 2 config
	EPwm2Regs.TBPRD = PWM_PRD; // Period = 1600 TBCLK counts
	EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
	EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
	EPwm2Regs.TBPHS.bit.TBPHS = 2; // Set Phase register to zero
	EPwm2Regs.TBCTL.bit.PHSDIR = 1;
	EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
	EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
	EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM2A
	EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
	EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Low complementary
	EPwm2Regs.DBFED = PWM_DB; // FED = 50 TBCLKs
	EPwm2Regs.DBRED = PWM_DB; // RED = 50 TBCLKs
	// EPWM Module 6 config
	EPwm6Regs.TBPRD = PWM_PRD; // Period = 1600 TBCLK counts
	EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
	EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;
	EPwm6Regs.TBPHS.bit.TBPHS = 2; // Set Phase register to zero
	EPwm6Regs.TBCTL.bit.PHSDIR = 1;
	EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm6Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
	EPwm6Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm6Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
	EPwm6Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm6Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	EPwm6Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm6Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm6Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPwm6A
	EPwm6Regs.AQCTLA.bit.CAD = AQ_CLEAR;
	EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Low complementary
	EPwm6Regs.DBFED = PWM_DB; // FED = 50 TBCLKs
	EPwm6Regs.DBRED = PWM_DB; // RED = 50 TBCLKs
	// EPWM Module 7 config
	EPwm7Regs.TBPRD = PWM_PRD; // Period = 1600 TBCLK counts
	EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
	EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;
	EPwm7Regs.TBPHS.bit.TBPHS = 2; // Set Phase register to zero
	EPwm7Regs.TBCTL.bit.PHSDIR = 1;
	EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm7Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
	EPwm7Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm7Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
	EPwm7Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm7Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	EPwm7Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm7Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm7Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3A
	EPwm7Regs.AQCTLA.bit.CAD = AQ_CLEAR;
	EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Low complementary
	EPwm7Regs.DBFED = PWM_DB; // FED = 50 TBCLKs
	EPwm7Regs.DBRED = PWM_DB; // RED = 50 TBCLKs
	// EPWM Module 8 config
	EPwm8Regs.TBPRD = PWM_PRD; // Period = 1600 TBCLK counts
	EPwm8Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
	EPwm8Regs.TBCTL.bit.CLKDIV = TB_DIV1;
	EPwm8Regs.TBPHS.bit.TBPHS = 2; // Set Phase register to zero
	EPwm8Regs.TBCTL.bit.PHSDIR = 1;
	EPwm8Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Symmetrical mode
	EPwm8Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
	EPwm8Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	EPwm8Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync flow-through
	EPwm8Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	EPwm8Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	EPwm8Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm8Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO; // load on CTR=Zero
	EPwm8Regs.AQCTLA.bit.CAU = AQ_SET; // set actions for EPWM3A
	EPwm8Regs.AQCTLA.bit.CAD = AQ_CLEAR;
	EPwm8Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
	EPwm8Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Low complementary
	EPwm8Regs.DBFED = PWM_DB; // FED = 50 TBCLKs
	EPwm8Regs.DBRED = PWM_DB; // RED = 50 TBCLKs
	// Run Time (Note: Example execution of one run-time instant)
	EALLOW;
	CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0x1;
	EDIS;
	//=========================================================
	EPwm2Regs.CMPA.bit.CMPA = 3000; // adjust duty for output EPWM1A
	EPwm6Regs.CMPA.bit.CMPA = 3000; // adjust duty for output EPWM2A
	EPwm7Regs.CMPA.bit.CMPA = 3000; // adjust duty for output EPWM3A
	EPwm8Regs.CMPA.bit.CMPA = 3000; // adjust duty for output EPWM3A
}

Hi Rahman,
Thank you so much your answer.