adc processing time?

Hi Joseph,

We specify the ADC timings in the datasheet in section 5.8.1.1.2 "ADC Timing Diagrams".

You select a row in the table based on the SYSCLK to ADCCLK divider ratio, and then the columns will tell you all the timings in SYSCLK cycles. The diagram also illustrates how back-to-back ADC conversion will occur.

The time for the ADC to process one conversion is longer than 11 SYSCLK cycles, so the total conversion time will be longer than 191ns. An easy sanity check is that if you use the minimum S+H duration, then 1/(time for 1 conversion) should approximately equal the maximum sample rate given in the datasheet first page.

S+H duration is dependent on accuracy, as per my understanding ?

can 3.1 MSPS be achieved by using the adc in the same module(ADCINA0, ADCINA1, ADCINA2, .....) when being sampled one after the other. 

is there separate sample and hold for each ADC modules (ADCINA,  ADCINB,....)?

Hi Joseph,

S+H duration can negatively impact accuracy if it is too low, but increasing the S+H duration won't increase accuracy if the settling is already sufficient. Basically you need to set the S+H duration long enough that the input signal will settle to within 1/4 LSBs or more during the S+H time. The TRM has a model of the ADC input, and also a formula you can use to roughly estimate the settling time. If you are using a low impedance driver for the ADC (<50 ohms or so) then you should be fine to just use the minimum S+H time given in the DS. Otherwise, if the signal source is higher impedance, you may need to adjust the S+H duration up.

Yes, 3.1MSPS can be achieved on a single ADC with back-to-back conversions.

Each ADC module has its own S+H and converter, so they can (and usually should) be used to process multiple voltages at the same time.

Thanks for the prompt reply,