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Sample and Hold timing after SOCA

Thomas Rae41
Prodigy 20 points

I am simultaneously sampling two signals.  SOCA goes low and I expect the sample and hold window to occur two adc cycles later and last for the period of time that I set(200ns).  I see the wave forms on the scope and the sample hold period is in correct position to correctly sample the pulse, but it does not. It seems the sample hold window occurs some 700ns later than it should.  I shut off all other ADC channels. Only two simultaneous samples triggered by a pwm compare and still 700ns later than the SOCA signal would indicate.

How can I accurately time my sample hold window? Other features claim 150ps resolution. This is way off.

  • 0
    TI__Guru 60865 points
    Hi Thomas,

    The ADC S+H window duration and position are ultimately controlled by ADCCLK; it won't be possible to position the S+H window with increased resolution using the HRPWM.

    How are you measuring the S+H position? The best way to do this is to keep very little capacitance on the ADC pin (~10pF), and then to also place a large series resistor between the signal source and the ADC pin (maybe ~50k). If you place a scope probe on the ADC pin, you should be able to observe the ADC inrush current directly, signifying the beginning of the S+H period. After the beginning of the S+H period, the ADC requires 13 ADCCLKs to process each conversion, and then if you trigger an interrupt after this I believe the context switch latency is about 16 SYSCLK cycles. If you then toggle a GPIO in the ISR there will be a couple more SYSCLK cycles of delay.