Configure SCI Tx with weak pull up. Shared SCI line Problem

Javier Alvarez

We have three TMS320F2837xS Delfino Microcontrollers communicated by serial. One is the master, the others are slaves (let's call them M, S1 and S2).

The two slaves share the same RX and TX lines (i.e. receive data from the master SCI, transmit to the same SCI).

When we have only one master and one slave, everything works as expected. However, when we connect two slaves, it seems that the TX line is pulled up while idle. This was confirmed with an oscilloscope. The TX bits sent by S1 range from 1.5V to 3.3V (instead of 0.0V to 3.3V).

I know we can configure the output as to have a weak pull-up, and we could solve our problem by configuring the GPIO as TX only when there's something to transmit, and change the configuration when there's nothing to be transmitted.

My question is, is it possible to configure the SCI TX line to have a weak pull-up to avoid switching the configuration of the GPIO every time?

Thanks

over 9 years ago

0 Javier Alvarez over 9 years ago

Prodigy 230 points

Just to clarify: when two slaves (S1 and S2) are connected, if S1 attempts to transmit and S2 is not transmitting, S2 would pull-up its output to 3.3V. Then every "low level" bit from S1 "adds" to the "high level" from S2, leaving us with the 1.5 V we're seing in the oscilloscope.

0 Sal Pezzino over 9 years ago in reply to Javier Alvarez

TI__Mastermind 32995 points

The problem may be that all three devices are pulling the slave TX pin high. What happens if only one device pulls the slave TX pin high?

sal

0 Javier Alvarez over 9 years ago in reply to Sal Pezzino

Prodigy 230 points

Thanks Sal,

Well, we only have two slaves, and yes, we know that one is pulling the TX pin high (since that's the default for idle in the tx pin) while the other is transmitting, hence the "half range" of the transmission.

I might be asking for too much, and should have a chip in the middle to allow for such changes instead. Or solve it by disabling the SCI TX by software, as we've been planning. I was just inquiring if there's a configuration on the GPIOs that would simplify this task.

Javier

0 Sal Pezzino over 9 years ago in reply to Javier Alvarez

TI__Mastermind 32995 points

Javier,

The TX pin will drive high. So you will have to change the MUX options when not transmitting in order to leave the pin floating or not driven high.

sal

0 Javier Alvarez over 9 years ago in reply to Sal Pezzino

Prodigy 230 points

I expected that much. Thanks for looking into this.

Regards

0 Cody Watkins over 9 years ago in reply to Javier Alvarez

TI__Mastermind 42195 points

Javier,

is my understanding of your system correct? See the first image below.

If so the you should be able to add an "and" gate on the RX line of the master. This will isolate S1 and S2 and allow either one to drive the bus to 0V. See image below.

Regards,
Cody

0 Cody Watkins over 9 years ago in reply to Cody Watkins

TI__Mastermind 42195 points

Note: This hardware workaround assumes that software will ensure that only one slave will write to the bus at a time. While sending messages from a slave the other should be pulling its TX pin "High". If both slaves try to write to the bus garbage data may appear, as either slave can force the bus "Low" independent of the other slave.

Cody

0 Javier Alvarez over 9 years ago in reply to Cody Watkins

Prodigy 230 points

I'm not sure if at this point of the development I'll be able to "ask" for an and gate. It simplifies the software, but complicates the hardware... In my experience, it's always the other way around: solve by software. But it's worth trying.

Thanks Cody.

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Configure SCI Tx with weak pull up. Shared SCI line Problem