single to differential THS4521 and TMS320F2837xS ADC

Hi Mark,

If doing a simple R-C on the input, there are basically two distinct options:

Charge sharing:

In this case, you put a really big capacitor right on the pin to supply all the input current to the ADC when sampling. Because all the charge comes from the external capacitor, it needs to be large enough that any inrush current to the ADC doesn't change the voltage more than the desired resolution. Therefore you would want the C on the pin to be at least 2^(N+2) times as large as the ADC Ch to get 1/4 LSBs settling. For 16-bit operation, ADC Ch is 16.5pF, so this would be 65536*4*16.5pF = 4.3uF, which is huge! Since all the charge comes from the low-impedance path of the capacitor, you can use the minimum ADC S+H window duration. From the ADCs perspective, the series R can be made as big as you want - this will reduce the LP filter cutoff frequency and help the op-amp with stability. In this case, with a 100 ohm series R and a 4.3uF capacitor, you would get a cutoff frequency around 740Hz (the filter is differential, so halve the capacitance when comparing to a single-ended filter).

Where you can run into issues here is actually the sample rate. Even though the voltage is only dropping by 1/4 LSBs each time (with the cap size chosen above) if the op-amp can't adequately recharge the cap between samples the voltage will slowly deplete over time. If you select 1/4LSBs as the additional droop error you are willing to tolerate, then the op-amp needs to recharge from (V - 1/2 LSBs) to (V - 1/4 LSBs) during the time between samples. This means you need to recharge halfway to the target voltage, or you need -ln(0.5) = 0.7 time constants. With 100 ohm series R and the cap chose above, Tau = 2.15E-6 * 100 = 215us. 0.7*215us = 150us. 1/150us = 6.6ksps maximum sample rate.

This should work well for you as long as the op-amp is stable with the large capacitance. You have a little margin still to increase R while still meeting the sample rate criteria. You could also halve the capacitance and accept 1 LSBs of total settling + droop error.

Non-charge sharing:

(In less detail)

For a higher sample rate, the op-amp needs to supply all the charge each time. In this case, you would probably use a capacitor in the pF range. Here, you need to use the equation (Rs+Ron)*Ch + Rs*Cp to find the settling time constant, and then ensure that the S+H window is long enough to allow adequate settling. At 16-bit resolution and for 1/4LSBs settling, you would want -ln((1/65536)*(1/4)) = 12.5 time constants.

The LP filter frequency will always be quite high. You can increase C and R to bring down the cutoff, but you will need to increase S+H duration to compensate. This won't get you anywhere near 100Hz (but as you said, you can do SW filtering instead).