HRPWM problem never solved

Hi Justin,

Have you tried running the HRPWM  example projects in controlSuite (http://www.ti.com/tool/controlsuite? These examples will allow you to run HRPWM with Autoconversion enabled and with it being disabled. This should provide a good reference on correct HRPWM register configuration.

Hrishi

Hi Hrishi!

I have! In fact, I've copied and pasted the HRPWM_Config function from hrpwm_duty_sfo_v8.c into my code and it does work! However, in neither the original ControlSuite program nor as implemented in my code can I do what I want to do.
I need to go down to zero duty cycle with HRPWM. In both of the cases above, I can go to maximum duty cycle without limitation, but not to zero. I don't need to go to maximum- I can deal with the limitation there, but I need to be precise down to zero.
I'm attempting the method described on pages 1865 and 1866 in the Technical Reference Manual. I've changed your code to look like this:

Uint16 j;
// ePWM channel register configuration with HRPWM
// ePWMxA / ePWMxB toggle low/high with MEP control on Rising edge

for (j=1;j<PWM_CH;j++)
{
(*ePWM[j]).TBCTL.bit.PRDLD = TB_SHADOW; // set Immediate load
(*ePWM[j]).TBPRD = PWMPer-1; // PWM frequency = 1 / period
(*ePWM[j]).CMPA.bit.CMPA = PWMPer / 2; // set duty 50% initially
(*ePWM[j]).CMPA.bit.CMPAHR = (1 << 8); // initialize HRPWM extension
(*ePWM[j]).CMPB.bit.CMPB = PWMPer / 2; // set duty 50% initially
(*ePWM[j]).CMPB.all |= (1 << 8); // initialize HRPWM extension
(*ePWM[j]).TBPHS.all = 0;
(*ePWM[j]).TBCTR = 0;

(*ePWM[j]).TBCTL.bit.CTRMODE = TB_COUNT_DOWN;
(*ePWM[j]).TBCTL.bit.PHSEN = TB_DISABLE;
(*ePWM[j]).TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;
(*ePWM[j]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[j]).TBCTL.bit.CLKDIV = TB_DIV1;
(*ePWM[j]).TBCTL.bit.FREE_SOFT = 11;

(*ePWM[j]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
(*ePWM[j]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
(*ePWM[j]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[j]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;


(*ePWM[j]).AQCTLA.bit.ZRO = AQ_CLEAR; // PWM toggle high/low
(*ePWM[j]).AQCTLA.bit.CAD = AQ_SET;
(*ePWM[j]).AQCTLB.bit.ZRO = AQ_SET;
(*ePWM[j]).AQCTLB.bit.CBD = AQ_CLEAR;

EALLOW;
(*ePWM[j]).HRCNFG.all = 0x0;
(*ePWM[j]).HRCNFG.bit.EDGMODE = HR_FEP; // FEP control on falling edge
(*ePWM[j]).HRCNFG.bit.CTLMODE = HR_CMP;
(*ePWM[j]).HRCNFG.bit.HRLOAD = HR_CTR_ZERO;
(*ePWM[j]).HRCNFG.bit.EDGMODEB = HR_FEP; // FEP control on falling edge
(*ePWM[j]).HRCNFG.bit.CTLMODEB = HR_CMP;
(*ePWM[j]).HRCNFG.bit.HRLOADB = HR_CTR_ZERO;

(*ePWM[j]).HRCNFG.bit.AUTOCONV = 1; // Enable auto-conversion logic

(*ePWM[j]).HRPCTL.bit.HRPE = 0; // Turn off high-resolution period control.
EDIS;

}


When I'm trying to edge down to zero, and EPwm1Regs.CMPA.bit.CMPA = 1, if autoconvert is turned on, EPwm1Regs.CMPA.bit.CMPAHR is ignored. When I have autoconvert turned off, the duty cycle gets larger as I increase CMPAHR. If I go to zero in CMPA and mess with CMPAHR, no value will produce any duty cycle above zero. Am I implementing the method described in the technical reference manual improperly?

Justin

Mistake! The Edgemode registers are REP, not FEP- sorry! The problem persists, though.

Hi Justin,

This is expected behavior. In high resolution mode the MEP is not active for the complete PWM period. This puts a restriction on minimum/maximum hi-res duty cycle ((TBCNT close to 0), and may also put a restriction on the maximum/minimum hi-res duty cycle (TBCNT close to TBPRD) depending on the operation mode and configuration. Please refer to the section titled 'Duty Cycle Range Limitation' in the technical reference manual (TRM) for more details.

Hrishi 

Hi Hrishi!

Thanks for responding so quickly!
In the TRM, on page 1855, it says :

If the application demands HRPWM operation below the minimum duty cycle limitation, then the HRPWM
can be configured to operate in count-down mode with the rising edge position (REP) controlled by the
MEP when high-resolution period is disabled (HRPCTL[HRPE] = 0). This is illustrated in Figure 15-8. In
this configuration, the minimum duty cycle limitation is no longer an issue. However, there will be a
maximum duty limitation with same percent numbers as given in Table 15-4.

Is there a way for me to operate down to zero duty cycle as described in the TRM or is this impossible?

Justin

Justin,

Yes this is possible as long as you avoid the hi-res edge from occurring in the restricted region (for proper hi-res operation) of the PWM period. In any case you will either have a minimum duty cycle limit or a maximum duty cycle limit or both with hi-res operation.

Hrishi

Hi Hrishi!

OK- I have it working, but not with the method described in the TRM. The code above sets the ramp to falling, PWM high on CMPA match ramp counting down, PWM low on ramp equal zero, rising edge MEP. This is the method described in the TRM, and I cannot get it to work.

The method that I used is rising ramp, PWM high on CMPA match ramp counting up, PWM low on ramp equal zero, rising edge MEP.

Has anyone at TI been able to get the TRM method working?

Thanks for your help Hrishi!

Justin