Hi,
I have used the sample code found in the technical reference guide to set up pwm 1, 2, and 3. Regardless of the values chosen for CMPx the duty cycle does not alter. I have a 90Mhz clock and want a 1kHz pwm.
EPwm1Regs.TBCTL.bit.CTRMODE =2;//asymmetrical upcount
EPwm1Regs.TBPRD = 45000; // Period = 45001 TBCLK counts assumes sysclkout=tbclk=90MHz
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Phase loading disabled
EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
EPwm1Regs.TBCTR=0;//clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV=0;//sysclk/1
EPwm1Regs.TBCTL.bit.CLKDIV=1;//sysclk/2
EPwm1Regs.CMPA.half.CMPA = 4500; //duty cycle
EPwm1Regs.AQCTLA.bit.PRD = 2; //EPWMA output high when counter equals the period
EPwm1Regs.AQCTLA.bit.CAU = 1; //EPWMA output low when counter equals CMPA on up count