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ADC MAX SAMPLE/CONVERT FOR 320F28069

PowerGuy
Intellectual 415 points


Hi,

I have a situation with the A/D and would like to verify if my assumptions are correct.

Currently I'm using a 320F28069 Piccolo.
I'm working at 90Mhz with ADC clock of 45Mhz.

I'm trying to sample and convert all 16 channels within 220Khz.

From the spec, I see the best/fastest way to accomplish this is using both sample&hold circuits with the overlap option on.

I have PWM3(220Khz) triggering the start of conversion.

Now,

To sample 16 channels using 2 S/H circuits @ 7 clocks per sample. ( 8 * 7 * (1/45Mhz) = 1.244uS

To convert would be 16 conversion and 13 clocks per conversion. (13 * 16 * (1/45Mhz) = 4.622uS  or 216Khz

Just from looking at the time it will take to preform the conversion, it seems impossible to do it under 220Khz.

Am I calculating things wrong ?

There are 4 AD inputs that I must sample and convert within 220Khz.
The rest can be done at 110Khz and maybe even 55Khz.

Do you have any recommendations ?
What other options do I have ?

  • 0
    TI__Guru 61235 points

    user4115707,

    Your calculations look correct.  The same number is arrived at using datasheet sprs698f, on the front page it says the ADC is "Up to 3.46 MSPS."  Divide this number by 16 channels, and you get 216.25 ksps/ch for 16 channels.

    You may be able to convert your 4 critical channels at 220 ksps, and the rest at 73.3 ksps by actively managing the ADC sequencer.  Call the critical channels # 0-3, and the rest are 4-15 of course.  Setup the ADC to trigger at 220 ksps (using a ePWM timer for example), and configure the sequencer for single sequencer with 8 conversions per trigger (MAXCONV=7).  You will get conversions of channels like this:

    1st trigger: 0,1,2,3,4,5,6,7

    2nd trigger: 0,1,2,3,8,9,10,11

    3rd trigger: 0,1,2,3,12,13,14,15

    This repeat from 1st trigger on your next trigger.

    You need to actively manage the sequencer channel selection registers each ADC interrupt (which you get after each group of 8 conversions).  You are using the sequencer in a Ping-Pong fashion to avoid race conditions.  Initially, the channel selection registers look like this:

    0,1,2,3,4,5,6,7,0,1,2,3,8,9,10,11

    In the 1st ISR, you have just converted the 1st half (0,1,2,3,4,5,6,7) and the ADC will convert the 2nd half on the next trigger (0,1,2,3,8,9,10,11).  In the ISR, change the channel selection regs to look like this:

    0,1,2,3,12,13,14,15,0,1,2,3,8,9,10,11

    I highlighted in yellow the channels that changed.

    In the next ISR, you will change the sequence to look like this:

    0,1,2,3,12,13,14,15,0,1,2,3,4,5,6,7

    and so on.  Get the picture?

    Regards,

    David

  • 0 in reply to David M. Alter
    Intellectual 415 points

    David,

    If I were to have my A/D set up for simultaneous sampling using both S/H cores, with a sampling Freq of 220Khz

    Can I sample SOC0-SOC2-SOC4-SOC8 in high priority mode and leave SOC10-SOC12-SOC14 a low priority ?

    My important A/D readings are in SOC2,SOC4,SOC6,SOC8 :

    SOC0 A5
      B5
    SOC2 A6
      B6
    SOC4 A0
      B0
    SOC6 A4
      B4
    SOC8 A2
      B2

    following the errata for the 28069, I've placed two non important readings in SOC0 (A5 and B5), so I can discard them.


    We are talking about sampling and converting 10 channels. That can be done within 220Khz.

    Then my questions are :

    What value do I use for the SOCPriority register?

    Do I use 0x09 ? since I'm using simultaneous mode and only even SOCs are looked at ? or 

    Set it to 0x0A for SOC0-SOC9?

    Also, what would be the update rate of the the low priority SOCs ?

    thanks

     

  • 0 in reply to PowerGuy
    TI__Guru 61235 points

    PowerGuy,

    Looking over my response from August 12, I see I was confusing the F2806x ADC with the older ADC front-end found on devices such as the F2833x.  My bad.

    I think yes, you can make SOC0 to SOC8 high priority, and make SOC10 to SOC14 low priority.  I'd trigger SOC10-12-14 from a different trigger (i.e., whatever slower sample rate you want, other than 220 kHz timer).

    I would set SOCPriority=0x9 (SOC0-8 hi pri).  Reading the user's guide, I guess you could also set it to 0xA.  Either should work.  But as you said, in simultaneous conversion mode we should normally think only of the even SOCs.  So, I'd use SOCPriority = 0x9.

    >> Also, what would be the update rate of the the low priority SOCs ?

    This is an interesting problem.  The ADC max sampling rate falls just short of what is needed to convert all 16 channels at 220 ksps.  Maybe you want to have the low-priority channels continuously convert?  You could trigger ADCINT1 or ADCINT2 at the end of SOC16, and use that to re-trigger SOC10.  That would keep the round-robin queue continusouly converting in the background as time permits.  When software read the results, they would get the latest conversion value.  This does not necessarily give you a constant sampling rate however, so it depends on your application.

    The other way to do it is to use slower triggers for the round-robin queue.  I would split the queue in two, with each piece fitting in the time remaining between the high-speed conversion group.  So, SOC10-12, and SOC14.  Setup two timers to trigger these at the end of the high-speed 220 ksps queue, and have the two triggers 180 deg out of phase.  Effectively, they will trigger at 440 kHz, and skew the timers by 180 degrees so that one triggers, then the high-pri group, then the other triggers, then the hi-pri group again, and so on.

    Just thinking out loud...

    Regards,

    David