Is a delay needed between setting and getting state of connected OUTPUT and INPUT?

cee

Intellectual 755 points

Hi,

This is my first project with a C2000, I have been using various other Microcontrollers.

I tried to set an OUTPUT, then read a connected INPUT right after. How fast is this possible?

Right now I have a huge delay loop (1'000'000 iterations) to make it work.

This is a stripped down example of my code:

EALLOW;

// input setup
GpioCtrlRegs.GPCPUD.bit.GPIO77 = 1;    // pullups mounted on board
GpioDataRegs.GPCCLEAR.bit.GPIO77 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO77 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO77 = 0;

// output setup
GpioCtrlRegs.GPCPUD.bit.GPIO73 = 1;
GpioDataRegs.GPCCLEAR.bit.GPIO73 = 1;
GpioCtrlRegs.GPCMUX1.bit.GPIO73 = 0;
GpioCtrlRegs.GPCDIR.bit.GPIO73 = 1;

EDIS;

// set output
GpioDataRegs.GPCSET.bit.GPIO73 = 1

// ...is a delay needed here?

if (GpioDataRegs.GPCDAT.bit.GPIO77)
    // output is set
else
    // output is cleared

over 9 years ago

0 Gautam Iyer over 9 years ago

Guru 192875 points

Hi cee,

Ideally next cycle itself you should be able to read but I would recommend 2-3 cycle delay.

Regards,
Gautam

0 Whitney Dewey over 9 years ago

TI__Guru 53775 points

Hello,

A million iterations IS huge. You'll need a delay but nothing that extreme. Does it make any difference if you use NOPs instead of a delay loop? Something like "__asm(" RPT #5 || NOP")" (you can change the 5 to some other number of repeats as needed--that's just what worked on my setup)?

What part number are you using? Are you using a custom board or one of TI's kits?

Thanks,
Whitney

0 Vivek Singh over 9 years ago in reply to Whitney Dewey

TI__Guru** 115271 points

Also please note that this delay will depend on the input qualification which is by default enabled. To reduce the delay, disable the input qualification.

Regards,

Vivek Singh

0 cee over 9 years ago in reply to Vivek Singh

Intellectual 755 points

Hi Vivek

Thanks for your answer.
As far as I understand, the input qualification (GPxQSEL1/2) does not apply to GPIO 64-79. Currently I am using GPIO 76|77.
According to SPRUFN1C (Delfino System Control and Interrupts Reference Guide) GPCDAT (read) is always sync'd with SYSCLK.

Are there other registers that need to be set correctly?

Best Regards,
cee

0 Vivek Singh over 9 years ago in reply to cee

TI__Guru** 115271 points

Cee,

You are right. On these pins there is no input qualification but still there is synchronizer which will take some additional cycle. So you have to add couple of NOPs before reading the status.

Regards,
Vivek Singh

0 Vivek Singh over 9 years ago in reply to Vivek Singh

TI__Guru** 115271 points

Cee, hope this issue is resolved.

0 cee over 9 years ago in reply to Vivek Singh

Intellectual 755 points

Hi Vivek,

Unfortunately I still have the huge delay as stated in my first post. It's an ugly hack but for now I moved on since this project was actually only to test another hardware and won't be used in production.

If anyone has some insight as to why my code behaves as it does, I am glad to give it another shot.

Thank you.

0 Vivek Singh over 9 years ago in reply to cee

TI__Guru** 115271 points

Cee,

Did you try the suggestion from Whitney of using NOP instead of loop ? If not then I would suggest to try that and let us know how many NOPs you have to use to make it working.

Regards,

Vivek Singh

0 Vivek Singh over 8 years ago in reply to Vivek Singh

TI__Guru** 115271 points

Hi Cee, Did you get chance to try NOPs, as suggested by Whitney?

0 Vivek Singh over 8 years ago in reply to Vivek Singh

TI__Guru** 115271 points

Closing the thread. If your issue is not resolved, please re-open the thread or start a new post.

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Is a delay needed between setting and getting state of connected OUTPUT and INPUT?