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PWM5 sync

PowerGuy
Intellectual 415 points

Currently I'm using a 320F28069 Piccolo.

I have PWMS1,2,3,4 running at 220Khz.

I need to have PWM5 running at 120Khz in sync with all other PWMS.

Per the tech reference manual, 3.3.4
"If synchronization is a requirement, ePWM module 2 can be configured as a slave and can operate at integer multiple (N) frequencies of module 1. The sync signal from master to slave ensures these modules remain locked"

Since PWM5 will be running slower than the other PWMs I cant use the Master/slave scheme.

Is the another way to sync PWM5 to PWMs 1,2,3 & 4 ?

  • 0
    TI__Guru 61235 points
    PowerGuy,

    Since all the PWMs run off the same clock (SYSCLKOUT), how about just starting them all at the same time using the TBCLKSYNC bit in PCLKCR0 register. Since they all run off the same clock, they will stay sync'd. Have all the PWMs configured, and then set TBCLKSYNC=1.

    Regards,
    David
  • 0 in reply to David M. Alter
    Intellectual 415 points
    So,

    this is the config I have;

    period variable is 409;
    PWM5 = period * 2;
    still PWM5 is not syncing to the other PWMs

    I would appreciate if you could give me some feedback on this.


    EALLOW;
    SysCtrlRegs.PCLKCR1.bit.EPWM1ENCLK = 1; // ePWM1
    SysCtrlRegs.PCLKCR1.bit.EPWM2ENCLK = 1; // ePWM2
    SysCtrlRegs.PCLKCR1.bit.EPWM3ENCLK = 1; // ePWM3
    SysCtrlRegs.PCLKCR1.bit.EPWM4ENCLK = 1; // ePWM4
    SysCtrlRegs.PCLKCR1.bit.EPWM5ENCLK = 1; // ePWM5
    SysCtrlRegs.PCLKCR1.bit.EPWM6ENCLK = 1; // ePWM6
    SysCtrlRegs.PCLKCR1.bit.EPWM7ENCLK = 1; // ePWM7
    SysCtrlRegs.PCLKCR1.bit.EPWM8ENCLK = 1; // ePWM8
    SysCtrlRegs.PCLKCR0.bit.HRPWMENCLK = 1; // HRPWM

    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

    EPwm1Regs.TBPRD = period; // 220Khz
    EPwm1Regs.TBPHS.half.TBPHS = 0; // Set Phase register to zero
    EPwm1Regs.TBCTR = 0;

    EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm1Regs.TBCTL.bit.PHSDIR = TB_SHADOW;
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    // Counter compare submodule registers
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPA.half.CMPA = 0;
    EPwm1Regs.CMPB = 0;

    // Action Qualifier SubModule Registers
    EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;
    EPwm1Regs.AQCTLA.bit.PRD = AQ_CLEAR;

    // DeadBand Control Register
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
    EPwm1Regs.DBRED = 0; // Initial value
    EPwm1Regs.DBFED = 0; // Initial value


    EPwm1Regs.AQCTLA.bit.ZRO = 2;
    EPwm1Regs.AQCTLA.bit.CAU = 1;
    EPwm1Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION; //
    EPwm1Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
    EPwm1Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
    EDIS;



    EALLOW;
    //Time Base SubModule Register

    EPwm2Regs.TBPRD = period;
    EPwm2Regs.TBPHS.half.TBPHS = 0;
    EPwm2Regs.TBCTR = 0;

    EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm2Regs.TBCTL.bit.PHSDIR = TB_SHADOW;
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;


    // Counter compare submodule registers
    EPwm2Regs.CMPA.half.CMPA = 0; // Initial value
    EPwm2Regs.CMPB = 0; // Initial value
    EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    // DeadBand Control Register
    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
    EPwm2Regs.DBRED = 0; // Initial value 1!!!
    EPwm2Regs.DBFED = 0; // Initial value

    // Action Qualifier SubModule Registers
    EPwm2Regs.AQCTLA.bit.ZRO = 2;
    EPwm2Regs.AQCTLA.bit.CAU = 1;
    EPwm2Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
    EPwm2Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
    EPwm2Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;

    EDIS;




    //Configure EPWM(n+2) time base for ADC SOC generation and syncing the DAC
    EALLOW;

    EPwm3Regs.TBPRD = period;
    EPwm3Regs.TBPHS.half.TBPHS = 0;
    EPwm3Regs.TBCTR = 0;

    EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm3Regs.TBCTL.bit.PHSDIR = TB_SHADOW;
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;


    // Counter compare submodule registers
    EPwm3Regs.CMPA.half.CMPA = 0; // Initial value
    EPwm3Regs.CMPB = 0; // Initial value
    EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    // DeadBand Control Register
    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
    EPwm3Regs.DBRED = 0; // Initial value 1!!!
    EPwm3Regs.DBFED = 0; // Initial value

    // Action Qualifier SubModule Registers
    EPwm3Regs.AQCTLA.bit.ZRO = 2;
    EPwm3Regs.AQCTLA.bit.CAU = 1;
    EPwm3Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
    EPwm3Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
    EPwm3Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;

    EDIS;

    /**************************************PWM4************************************************************/
    //Time Base SubModule Register

    EALLOW;
    EPwm4Regs.TBPRD = period;
    EPwm4Regs.TBPHS.half.TBPHS = 0;
    EPwm4Regs.TBCTR = 0;


    EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; //
    EPwm4Regs.TBCTL.bit.PHSDIR = TB_SHADOW;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    // Counter compare submodule registers
    EPwm4Regs.CMPA.half.CMPA = 0; // Initial value
    EPwm4Regs.CMPB = 0; // Initial value
    EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    // DeadBand Control Register
    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
    EPwm4Regs.DBRED = 0; //
    EPwm4Regs.DBFED = 0; //

    // Action Qualifier SubModule Registers
    EPwm4Regs.AQCTLA.bit.ZRO = 2;
    EPwm4Regs.AQCTLA.bit.CAU = 1;
    EPwm4Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
    EPwm4Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
    EPwm4Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;

    EDIS;

    // PWM 5 runs at 110Khz to trigger A/D

    EALLOW;
    EPwm5Regs.TBPRD = period*2;
    EPwm5Regs.TBPHS.half.TBPHS = 0;
    EPwm5Regs.TBCTR = 0;

    EPwm5Regs.TBCTL.bit.PRDLD = TB_SHADOW;
    EPwm5Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm5Regs.TBCTL.bit.PHSEN = TB_ENABLE;
    EPwm5Regs.TBCTL.bit.PHSDIR = TB_SHADOW;
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;


    // Counter compare submodule registers
    EPwm5Regs.CMPA.half.CMPA = 0; // Initial value
    EPwm5Regs.CMPB = 0; // Initial value
    EPwm5Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm5Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm5Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
    EPwm5Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

    // DeadBand Control Register
    EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi Complimentary
    EPwm5Regs.DBRED = 0; // Initial value 1!!!
    EPwm5Regs.DBFED = 0; // Initial value

    // Action Qualifier SubModule Registers
    EPwm5Regs.AQCTLA.bit.ZRO = 2;
    EPwm5Regs.AQCTLA.bit.CAU = 1;
    EPwm5Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
    EPwm5Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
    EPwm5Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;



    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;



    EDIS;
  • 0 in reply to PowerGuy
    Intellectual 415 points
    yay!
    got it!
    just needed to use clk_div on pwm5!


    EPwm5Regs.TBCTL.bit.PHSDIR = TB_SHADOW;
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV2;

    now everything's synced!