Other Parts Discussed in Thread: SM320F2812
Hi,
We are using the SM320F2812 DSP 1.8V CORE BGA179
How much slower would a MRAM (50n read access time) connected to the external bus interface bevs using the pipelined internal flash?
The SW Engineer says about 6 times slower with the MRAM when used as CODE memory vs pipelined internal flash used as CODE memory.
What could be expexted ? We use a 40MHz external oscillator
We use the internal PLL to take that up to 80Mhz
These are the configuration parameter we use ..
X2TIMING 0 Timing values are scaled 1:1
XSIZE 11 No other value supported
READYMODE 1 XREADY input is asynchronous
USEREADY 0 XREADY input is ignored
XRDLEAD 01 LR = 1 x 1 x 25 = 25 ns
XRDACTIVE 001 AR = (1 x 1 + 1) x 25 = 50 ns
XRDTRAIL 01 TR = 1 x 1 x 25 = 25 ns
XWRLEAD 01 LW = 1 x 1 x 25 = 25 ns
XWRACTIVE 000 AW = (1 x 0 + 1) x 25 = 25 ns
XWRTRAIL 01 TW = 1 x 1 x 25 = 25 ns
