It states (example 5-2 spruHM8e)
MOV MAR0, #_X
I1-oldMAR0 will be used if use instruction here that uses it
I2- old MAR0 will be used if use instruction here that uses it
I3-cant use MAR0
I4- new MAR0 available for use
but could I do: (to swap MAR0 as quickly as possible in this example)
MOV MAR0, #_X
I1 - some instruction using old MAR0
I2 - MOV MAR0, #_Y
I3-I1 some instruction that doesn't use MAR0
I4-I2 - some instruction that uses MAR0 that desire _X location
I5-I3 - some instruction that doesn't use MAR0 since _Y switch will be at I3 equivalent
I6-I4 - MOV MAR0, #_X
I1-I5 - some instruction that desire _Y location
I2-I6 - MOV MAR0, #_Y
I3-I1 some instruction that doesn't use MAR0
...
pattern repeats.
ALSO... how does loading the MAR register work in branches?
so if I have a branch do I just count the cycles the same way relative to where the branch goes?
one possible example is: (assume for now this is just a for loop, so assume the branch for now always branches to loop till the counter decrements to zero)
loop:
SomeTest to set flag
MNOP ( or other instructions..)
MNOP
MNOP
MBNCDD loop, NEQ
MNOP
MNOP
MOV MAR0, #_Var
would this loop be interpreted as counting cycle I1 I2 etc as shown below after the first time it hits the load MAR0?
loop:
I1 - Instruction test flag
I2 - instruction can use old MAR0
I3 - instruction no use MAR0
I4 - instruction use new MAR0
I5 - Branch instruction
I6 - ?
I7 - ?
I8 - MOV MAR0, #_Var
So of course the idea is to flip flop the MAR0 in the tightest loop possible in a branch.. so just want to be sure This is how to count how the pipeline works in this case.
A third part to this question is with regard to the read after a write.
If I am essentially loading an MAR register, using it with post increment, writing it back, flopping to the other one, using it, post incrementing it, storing it...
So just combining the loading of MAR0 and the writing for now (not the branch)
If I did
MOV MAR0, _X
I1-
I2-
I3-
I4 - MOV MAR0 _Y
I5-I1- use MAR0 with post ++ on _X
I6-I2 - write MAR0 back to location _X
I7-I3 -WX1
I8 - I4-WX2 use MAR0 with post ++ on _Y
I9-I5-WX3 write MAR0 back to location _Y
I10-I6-WX4-WY1 MOV MAR0 _X (First chance to read it because need to wait to WX4 after write to ensure write is complete before reading from same memory, correct?)
cycle could continue...
Just want to be sure this is the correct thinking... both in terms of making sure I wait for the MAR# register and to wait for the reading of the same memory location after just writing the post incremented value to it.
I realize there is a MMOV16 MARx, MRa, #16 command so I don't have to read and write to memory, I could use two registers to hold the MAR values, increment the registers, but assuming I did the memory method.
Could you also comment on what is meant by the branch instruction has 1-7 cycle count? with regard to MNOPs? The documentation isn't clear on that.
MNOP
MNOP
MNOP
Branch
MNOP
MNOP
MNOP
Is it saying this executes in 1 cycle? its a bit confusing what it means.
Thanks.
