Other Parts Discussed in Thread: TMS320F28377S
Hello,
I have a custom board with the TMS320F28377S processor. The ADC values are not consistent when I start up the processor. According to the watch window, they will start up with an offset of +/- 50 units from previous runs.
My ADCs are initialized as follows:
void ConfigureADC(void)
{
//Write ADC configurations and power up the ADC for both ADC A
Uint16 i;
EALLOW;
//write configurations for ADC-A
// External REFERENCE must be provided
AdcaRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4 - max is 50 MHz from table 5.43 in www.ti.com/lit/ds/symlink/tms320f28377s.pdf
// also see table 9-14 in www.ti.com/.../spruhx5c.pdf for codes/values to get divisors
AdcSetMode(ADC_ADCA,RESOLUTION_12BIT,SIGNAL_SINGLE);
//Set pulse positions to late - ADC interrupt happens after result0 should be valid
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//write configurations for ADC-B
// External REFERENCE must be provided
AdcbRegs.ADCCTL2.bit.PRESCALE = 6; //set ADCCLK divider to /4
AdcSetMode(ADC_ADCB,RESOLUTION_12BIT,SIGNAL_SINGLE);
//Set pulse positions to late - ADC interrupt happens after Result0 should be valid
AdcbRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//power up the ADC
AdcbRegs.ADCCTL1.bit.ADCPWDNZ = 1;
//delay for > 1ms to allow ADC time to power up
for(i = 0; i < 1000; i++){
asm(" RPT#255 || NOP");
}
EDIS;
}
and the ADCs I am reading are:
// EPWM3 trigger channels (Resolver) // Resolver channels run at higher (synchronous demod) frequency on ADC A channel SOC0, SOC1 // For resolver these were triggered off ePWM3 SOCa to be synchronous with ePWM3 that would generate resolver excitation // For GL-10 gen we are just using these inputs as analog bus measurements, so we will trigger them off ePWM7 like the rest of the system // Resolver Fbk - sine @ A0 (GENSET - BUS_V) // ******************************** AdcaRegs.ADCSOC0CTL.bit.CHSEL = 0; // aSOC0 will convert pin A0 AdcaRegs.ADCSOC0CTL.bit.ACQPS = 30; // sample window in SYSCLK cycles (or ADCCLK cycles?) // AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 9; // trigger on ePWM3 SOCA AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 0x11; // trigger on ePWM7 SOCA for GL-10 gen // Resolver Fbk - cos @ A1 (GENSET - ALT_CS) // ******************************** AdcaRegs.ADCSOC1CTL.bit.CHSEL = 15; // aSOC1 will convert pin A15 **(A1 on AFIO board connected to A15 on CPU board thru 40pin connector)** AdcaRegs.ADCSOC1CTL.bit.ACQPS = 30; // sample window in SYSCLK cycles // AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 9; // trigger on ePWM3 SOCA AdcaRegs.ADCSOC1CTL.bit.TRIGSEL = 0x11; // trigger on ePWM7 SOCA for GL-10 gen // Batt current @ B0 (GENSET - BAT_CS) AdcbRegs.ADCSOC0CTL.bit.CHSEL = 0; // bSOC0 will convert pin B0 AdcbRegs.ADCSOC0CTL.bit.ACQPS = 30; // sample window in SYSCLK cycles AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 0x11; // trigger on ePWM7 SOCA
Has anyone had a startup offset problem like this before? The offset seems random and inconsistent. From the technical reference manual, there is some info on zero offset calibration, but I'm not sure if I completely understand how to implement it. Is there any example code for this processor for zero offset calibration? Sometimes, a grounded pin will read ~10-20 in the ADC result register.
Any help is appreciated - I've been trying to troubleshoot this for over 3 months!
