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TMS320C28346: PLL block diagram

Hideaki Nambu
Mastermind 9165 points

Hello,

Are there any materials which show a block diagram of the PLL inside ?

'PLL' boxes were found in the datasheet and and reference guide SPRUFN1C.pdf, but my customer asked the inside the box.

Me and my customer are doing a review of the clock tree.

-n

  • 0
    TI__Expert 8950 points

    A phase-locked loop (PLL) is basically a voltage-controlled oscillator with a feedback loop that determines the output frequency and phase relative to an input clock. Here's a generic block diagram:


  • 0 in reply to Adam Haun
    Mastermind 9165 points
    Adam,
    My customer asked the loop filter time-constant. Could you please tell us ?
    In the customer board their external clock generator is concerned about its stability, therefore we are talking about the impact to the PLL output frequency. Their XCLKIN is 30MHz. PLL multiplies x20 to 600MHz. Then divides by 2 to 300MHz.

    -n
  • 0 in reply to Hideaki Nambu
    TI__Expert 5240 points

    Hello,

    As long as the clock input and output are kept within the specified datasheet range there will not be any stability issues.  We do recommend using a good quality clock source for the input.  If a poor clock source which varies widely or skips clocks is used as the reference clock then the PLL output will also be poor in quality.

    Best regards,
    Jason