TMS320F2808 DSP power-on time

Not sure why the following didn't post originally after the "...I believe it is ok based on the following:..."

3.2 Reset and Watchdog

The XRS pin facilitates the device reset (in) and watchdog reset (out) signals. A warm reset pulse-width is

specified as eight times the oscillator clock (OSCCLK) period; however, the power on reset’s pulse-width

has to be much longer to account for the time required for VDD to reach 1.5 V (to enhance Flash reliability)

and the oscillator start-up period of 10 mS (nominal). You may prefer to keep this duration in excess of

100 ms to overcome any other related delays.

During power down, the XRS pin must be pulled low at least 8 μs prior to VDD reaching 1.5 V to enhance

Flash reliability.

Whenever the 8-bit watchdog up counter has reached its maximum value, the watchdog module

generates an output pulse 512 oscillator clocks wide. Note that the WDRST signal outputs the reset signal

over the XRS pin. The output buffer of this pin is an open-drain with an internal pullup (100 uA, typical); it

is recommended that the open-drain device drive this pin. Figure 5 illustrates a block diagram of the

watchdog module.

Saurabh,

I do not see a scope capture in your post. Also, if you are quoting something from our docs, please include the literature number/page number etc. Could you please re-post with the missing information? Reading your post, it is not clear what part of the post is a quote from our documentation.

dsp_init_time (timing capture of xrs).pdf

Hi Hareesh,

Sorry for leaving out important info.  

I'm referencing Section 3.2: Reset and Watchdog from the following document:

SPRAAS1C "Handling of Different Hardware Building Blocks"

I'm hoping the scope capture actually attaches this time and hopefully you can see it ok.

The signal in blue is the /XRS (device reset) while the signal in red is a gpio I'm toggling for timing capture purposes. 

1. The first time the GPIO goes high is at power up

2. /XRS is held low for about 115ms

3. When the GPIO goes low (after /XRS goes high), that is the point I execute the first line in main() of the application sw.

4.  There is a point at which /XRS goes low again but that is expected due to the watchdog test I'm executing.

Can you confirm the time of the /XRS pin being held low at startup is as expected? 

If needed, is it possible to safely reduce the time by say about 20-50ms? 

Thanks!

Saurabh